module QueueCompatibility_2(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input  [1:0] io_enq_bits,
  input        io_deq_ready,
  output       io_deq_valid,
  output [1:0] io_deq_bits
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] ram [0:1]; // @[Decoupled.scala 275:95]
  wire  ram_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_MPORT_en; // @[Decoupled.scala 275:95]
  reg  enq_ptr_value; // @[Counter.scala 61:40]
  reg  deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_12 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_12 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_io_deq_bits_MPORT_en = 1'h1;
  assign ram_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_io_deq_bits_MPORT_data = ram[ram_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_MPORT_data = io_enq_bits;
  assign ram_MPORT_addr = enq_ptr_value;
  assign ram_MPORT_mask = 1'h1;
  assign ram_MPORT_en = empty ? _GEN_12 : _do_enq_T;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits = empty ? io_enq_bits : ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_MPORT_en & ram_MPORT_mask) begin
      ram[ram_MPORT_addr] <= ram_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= enq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 1'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= deq_ptr_value + 1'h1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram[initvar] = _RAND_0[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  enq_ptr_value = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  deq_ptr_value = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AXI4Xbar(
  input         clock,
  input         reset,
  output        auto_in_1_aw_ready,
  input         auto_in_1_aw_valid,
  input         auto_in_1_aw_bits_id,
  input  [11:0] auto_in_1_aw_bits_addr,
  input  [7:0]  auto_in_1_aw_bits_len,
  input  [2:0]  auto_in_1_aw_bits_size,
  input  [1:0]  auto_in_1_aw_bits_burst,
  input  [3:0]  auto_in_1_aw_bits_echo_tl_state_size,
  input  [1:0]  auto_in_1_aw_bits_echo_tl_state_source,
  output        auto_in_1_w_ready,
  input         auto_in_1_w_valid,
  input  [31:0] auto_in_1_w_bits_data,
  input  [3:0]  auto_in_1_w_bits_strb,
  input         auto_in_1_w_bits_last,
  input         auto_in_1_b_ready,
  output        auto_in_1_b_valid,
  output [1:0]  auto_in_1_b_bits_resp,
  output [3:0]  auto_in_1_b_bits_echo_tl_state_size,
  output [1:0]  auto_in_1_b_bits_echo_tl_state_source,
  output        auto_in_1_ar_ready,
  input         auto_in_1_ar_valid,
  input         auto_in_1_ar_bits_id,
  input  [11:0] auto_in_1_ar_bits_addr,
  input  [7:0]  auto_in_1_ar_bits_len,
  input  [2:0]  auto_in_1_ar_bits_size,
  input  [1:0]  auto_in_1_ar_bits_burst,
  input  [3:0]  auto_in_1_ar_bits_echo_tl_state_size,
  input  [1:0]  auto_in_1_ar_bits_echo_tl_state_source,
  input         auto_in_1_r_ready,
  output        auto_in_1_r_valid,
  output [31:0] auto_in_1_r_bits_data,
  output [1:0]  auto_in_1_r_bits_resp,
  output [3:0]  auto_in_1_r_bits_echo_tl_state_size,
  output [1:0]  auto_in_1_r_bits_echo_tl_state_source,
  output        auto_in_1_r_bits_last,
  output        auto_in_0_aw_ready,
  input         auto_in_0_aw_valid,
  input  [11:0] auto_in_0_aw_bits_addr,
  input  [7:0]  auto_in_0_aw_bits_len,
  input  [2:0]  auto_in_0_aw_bits_size,
  input  [1:0]  auto_in_0_aw_bits_burst,
  input  [3:0]  auto_in_0_aw_bits_echo_tl_state_size,
  input  [1:0]  auto_in_0_aw_bits_echo_tl_state_source,
  output        auto_in_0_w_ready,
  input         auto_in_0_w_valid,
  input  [31:0] auto_in_0_w_bits_data,
  input  [3:0]  auto_in_0_w_bits_strb,
  input         auto_in_0_w_bits_last,
  input         auto_in_0_b_ready,
  output        auto_in_0_b_valid,
  output [1:0]  auto_in_0_b_bits_resp,
  output [3:0]  auto_in_0_b_bits_echo_tl_state_size,
  output [1:0]  auto_in_0_b_bits_echo_tl_state_source,
  output        auto_in_0_ar_ready,
  input         auto_in_0_ar_valid,
  input  [11:0] auto_in_0_ar_bits_addr,
  input  [7:0]  auto_in_0_ar_bits_len,
  input  [2:0]  auto_in_0_ar_bits_size,
  input  [1:0]  auto_in_0_ar_bits_burst,
  input  [3:0]  auto_in_0_ar_bits_echo_tl_state_size,
  input  [1:0]  auto_in_0_ar_bits_echo_tl_state_source,
  input         auto_in_0_r_ready,
  output        auto_in_0_r_valid,
  output [31:0] auto_in_0_r_bits_data,
  output [1:0]  auto_in_0_r_bits_resp,
  output [3:0]  auto_in_0_r_bits_echo_tl_state_size,
  output [1:0]  auto_in_0_r_bits_echo_tl_state_source,
  output        auto_in_0_r_bits_last,
  input         auto_out_aw_ready,
  output        auto_out_aw_valid,
  output        auto_out_aw_bits_id,
  output [11:0] auto_out_aw_bits_addr,
  output [7:0]  auto_out_aw_bits_len,
  output [2:0]  auto_out_aw_bits_size,
  output [1:0]  auto_out_aw_bits_burst,
  output [3:0]  auto_out_aw_bits_echo_tl_state_size,
  output [1:0]  auto_out_aw_bits_echo_tl_state_source,
  input         auto_out_w_ready,
  output        auto_out_w_valid,
  output [31:0] auto_out_w_bits_data,
  output [3:0]  auto_out_w_bits_strb,
  output        auto_out_w_bits_last,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input         auto_out_b_bits_id,
  input  [1:0]  auto_out_b_bits_resp,
  input  [3:0]  auto_out_b_bits_echo_tl_state_size,
  input  [1:0]  auto_out_b_bits_echo_tl_state_source,
  input         auto_out_ar_ready,
  output        auto_out_ar_valid,
  output        auto_out_ar_bits_id,
  output [11:0] auto_out_ar_bits_addr,
  output [7:0]  auto_out_ar_bits_len,
  output [2:0]  auto_out_ar_bits_size,
  output [1:0]  auto_out_ar_bits_burst,
  output [3:0]  auto_out_ar_bits_echo_tl_state_size,
  output [1:0]  auto_out_ar_bits_echo_tl_state_source,
  output        auto_out_r_ready,
  input         auto_out_r_valid,
  input         auto_out_r_bits_id,
  input  [31:0] auto_out_r_bits_data,
  input  [1:0]  auto_out_r_bits_resp,
  input  [3:0]  auto_out_r_bits_echo_tl_state_size,
  input  [1:0]  auto_out_r_bits_echo_tl_state_source,
  input         auto_out_r_bits_last
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  awOut_0_clock; // @[Xbar.scala 63:47]
  wire  awOut_0_reset; // @[Xbar.scala 63:47]
  wire  awOut_0_io_enq_ready; // @[Xbar.scala 63:47]
  wire  awOut_0_io_enq_valid; // @[Xbar.scala 63:47]
  wire [1:0] awOut_0_io_enq_bits; // @[Xbar.scala 63:47]
  wire  awOut_0_io_deq_ready; // @[Xbar.scala 63:47]
  wire  awOut_0_io_deq_valid; // @[Xbar.scala 63:47]
  wire [1:0] awOut_0_io_deq_bits; // @[Xbar.scala 63:47]
  wire  requestROI_0_1 = ~auto_out_r_bits_id; // @[Parameters.scala 46:9]
  wire  requestBOI_0_1 = ~auto_out_b_bits_id; // @[Parameters.scala 46:9]
  reg  latched; // @[Xbar.scala 165:30]
  wire  _bundleOut_0_aw_valid_T = latched | awOut_0_io_enq_ready; // @[Xbar.scala 166:59]
  reg  awOut_0_io_enq_bits_idle; // @[Xbar.scala 249:23]
  wire  awOut_0_io_enq_bits_anyValid = auto_in_0_aw_valid | auto_in_1_aw_valid; // @[Xbar.scala 253:36]
  reg  awOut_0_io_enq_bits_state_0; // @[Xbar.scala 268:24]
  reg  awOut_0_io_enq_bits_state_1; // @[Xbar.scala 268:24]
  wire  _awOut_0_io_enq_bits_out_0_aw_valid_T_2 = awOut_0_io_enq_bits_state_0 & auto_in_0_aw_valid |
    awOut_0_io_enq_bits_state_1 & auto_in_1_aw_valid; // @[Mux.scala 27:73]
  wire  out_0_aw_valid = awOut_0_io_enq_bits_idle ? awOut_0_io_enq_bits_anyValid :
    _awOut_0_io_enq_bits_out_0_aw_valid_T_2; // @[Xbar.scala 285:22]
  wire  out_0_aw_ready = auto_out_aw_ready & _bundleOut_0_aw_valid_T; // @[Xbar.scala 167:47]
  wire  _T = awOut_0_io_enq_ready & awOut_0_io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_0 = _T | latched; // @[Xbar.scala 165:30 169:{39,49}]
  wire  _T_1 = out_0_aw_ready & out_0_aw_valid; // @[Decoupled.scala 52:35]
  wire  out_0_w_valid = awOut_0_io_deq_bits[0] & auto_in_0_w_valid | awOut_0_io_deq_bits[1] & auto_in_1_w_valid; // @[Mux.scala 27:73]
  wire  out_0_w_ready = auto_out_w_ready & awOut_0_io_deq_valid; // @[Xbar.scala 174:45]
  wire  out_0_w_bits_last = awOut_0_io_deq_bits[0] & auto_in_0_w_bits_last | awOut_0_io_deq_bits[1] &
    auto_in_1_w_bits_last; // @[Mux.scala 27:73]
  wire  portsRIO_filtered_0_valid = auto_out_r_valid & auto_out_r_bits_id; // @[Xbar.scala 229:40]
  wire  portsRIO_filtered_1_valid = auto_out_r_valid & requestROI_0_1; // @[Xbar.scala 229:40]
  wire  portsBIO_filtered_0_valid = auto_out_b_valid & auto_out_b_bits_id; // @[Xbar.scala 229:40]
  wire  portsBIO_filtered_1_valid = auto_out_b_valid & requestBOI_0_1; // @[Xbar.scala 229:40]
  wire [1:0] awOut_0_io_enq_bits_readys_valid = {auto_in_1_aw_valid,auto_in_0_aw_valid}; // @[Cat.scala 33:92]
  wire  _awOut_0_io_enq_bits_readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
  reg [1:0] awOut_0_io_enq_bits_readys_mask; // @[Arbiter.scala 23:23]
  wire [1:0] _awOut_0_io_enq_bits_readys_filter_T = ~awOut_0_io_enq_bits_readys_mask; // @[Arbiter.scala 24:30]
  wire [1:0] _awOut_0_io_enq_bits_readys_filter_T_1 = awOut_0_io_enq_bits_readys_valid &
    _awOut_0_io_enq_bits_readys_filter_T; // @[Arbiter.scala 24:28]
  wire [3:0] awOut_0_io_enq_bits_readys_filter = {_awOut_0_io_enq_bits_readys_filter_T_1,auto_in_1_aw_valid,
    auto_in_0_aw_valid}; // @[Cat.scala 33:92]
  wire [3:0] _GEN_16 = {{1'd0}, awOut_0_io_enq_bits_readys_filter[3:1]}; // @[package.scala 253:43]
  wire [3:0] _awOut_0_io_enq_bits_readys_unready_T_1 = awOut_0_io_enq_bits_readys_filter | _GEN_16; // @[package.scala 253:43]
  wire [3:0] _awOut_0_io_enq_bits_readys_unready_T_4 = {awOut_0_io_enq_bits_readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
  wire [3:0] _GEN_17 = {{1'd0}, _awOut_0_io_enq_bits_readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
  wire [3:0] awOut_0_io_enq_bits_readys_unready = _GEN_17 | _awOut_0_io_enq_bits_readys_unready_T_4; // @[Arbiter.scala 25:58]
  wire [1:0] _awOut_0_io_enq_bits_readys_readys_T_2 = awOut_0_io_enq_bits_readys_unready[3:2] &
    awOut_0_io_enq_bits_readys_unready[1:0]; // @[Arbiter.scala 26:39]
  wire [1:0] awOut_0_io_enq_bits_readys_readys = ~_awOut_0_io_enq_bits_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire [1:0] _awOut_0_io_enq_bits_readys_mask_T = awOut_0_io_enq_bits_readys_readys & awOut_0_io_enq_bits_readys_valid; // @[Arbiter.scala 28:29]
  wire [2:0] _awOut_0_io_enq_bits_readys_mask_T_1 = {_awOut_0_io_enq_bits_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _awOut_0_io_enq_bits_readys_mask_T_3 = _awOut_0_io_enq_bits_readys_mask_T |
    _awOut_0_io_enq_bits_readys_mask_T_1[1:0]; // @[package.scala 244:43]
  wire  awOut_0_io_enq_bits_readys_0 = awOut_0_io_enq_bits_readys_readys[0]; // @[Xbar.scala 255:69]
  wire  awOut_0_io_enq_bits_readys_1 = awOut_0_io_enq_bits_readys_readys[1]; // @[Xbar.scala 255:69]
  wire  awOut_0_io_enq_bits_winner_0 = awOut_0_io_enq_bits_readys_0 & auto_in_0_aw_valid; // @[Xbar.scala 257:63]
  wire  awOut_0_io_enq_bits_winner_1 = awOut_0_io_enq_bits_readys_1 & auto_in_1_aw_valid; // @[Xbar.scala 257:63]
  wire  awOut_0_io_enq_bits_muxState_0 = awOut_0_io_enq_bits_idle ? awOut_0_io_enq_bits_winner_0 :
    awOut_0_io_enq_bits_state_0; // @[Xbar.scala 269:23]
  wire  awOut_0_io_enq_bits_muxState_1 = awOut_0_io_enq_bits_idle ? awOut_0_io_enq_bits_winner_1 :
    awOut_0_io_enq_bits_state_1; // @[Xbar.scala 269:23]
  wire  _GEN_3 = awOut_0_io_enq_bits_anyValid ? 1'h0 : awOut_0_io_enq_bits_idle; // @[Xbar.scala 273:21 249:23 273:28]
  wire  _GEN_4 = _T_1 | _GEN_3; // @[Xbar.scala 274:{24,31}]
  wire  awOut_0_io_enq_bits_allowed_0 = awOut_0_io_enq_bits_idle ? awOut_0_io_enq_bits_readys_0 :
    awOut_0_io_enq_bits_state_0; // @[Xbar.scala 277:24]
  wire  awOut_0_io_enq_bits_allowed_1 = awOut_0_io_enq_bits_idle ? awOut_0_io_enq_bits_readys_1 :
    awOut_0_io_enq_bits_state_1; // @[Xbar.scala 277:24]
  wire [1:0] _awOut_0_io_enq_bits_T_17 = awOut_0_io_enq_bits_muxState_0 ? auto_in_0_aw_bits_echo_tl_state_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _awOut_0_io_enq_bits_T_18 = awOut_0_io_enq_bits_muxState_1 ? auto_in_1_aw_bits_echo_tl_state_source : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _awOut_0_io_enq_bits_T_20 = awOut_0_io_enq_bits_muxState_0 ? auto_in_0_aw_bits_echo_tl_state_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _awOut_0_io_enq_bits_T_21 = awOut_0_io_enq_bits_muxState_1 ? auto_in_1_aw_bits_echo_tl_state_size : 4'h0; // @[Mux.scala 27:73]
  wire [1:0] _awOut_0_io_enq_bits_T_35 = awOut_0_io_enq_bits_muxState_0 ? auto_in_0_aw_bits_burst : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _awOut_0_io_enq_bits_T_36 = awOut_0_io_enq_bits_muxState_1 ? auto_in_1_aw_bits_burst : 2'h0; // @[Mux.scala 27:73]
  wire [2:0] _awOut_0_io_enq_bits_T_38 = awOut_0_io_enq_bits_muxState_0 ? auto_in_0_aw_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _awOut_0_io_enq_bits_T_39 = awOut_0_io_enq_bits_muxState_1 ? auto_in_1_aw_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [7:0] _awOut_0_io_enq_bits_T_41 = awOut_0_io_enq_bits_muxState_0 ? auto_in_0_aw_bits_len : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _awOut_0_io_enq_bits_T_42 = awOut_0_io_enq_bits_muxState_1 ? auto_in_1_aw_bits_len : 8'h0; // @[Mux.scala 27:73]
  wire [11:0] _awOut_0_io_enq_bits_T_44 = awOut_0_io_enq_bits_muxState_0 ? auto_in_0_aw_bits_addr : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] _awOut_0_io_enq_bits_T_45 = awOut_0_io_enq_bits_muxState_1 ? auto_in_1_aw_bits_addr : 12'h0; // @[Mux.scala 27:73]
  reg  idle; // @[Xbar.scala 249:23]
  wire  anyValid = auto_in_0_ar_valid | auto_in_1_ar_valid; // @[Xbar.scala 253:36]
  wire [1:0] readys_valid = {auto_in_1_ar_valid,auto_in_0_ar_valid}; // @[Cat.scala 33:92]
  reg [1:0] readys_mask; // @[Arbiter.scala 23:23]
  wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
  wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
  wire [3:0] readys_filter = {_readys_filter_T_1,auto_in_1_ar_valid,auto_in_0_ar_valid}; // @[Cat.scala 33:92]
  wire [3:0] _GEN_18 = {{1'd0}, readys_filter[3:1]}; // @[package.scala 253:43]
  wire [3:0] _readys_unready_T_1 = readys_filter | _GEN_18; // @[package.scala 253:43]
  wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
  wire [3:0] _GEN_19 = {{1'd0}, _readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
  wire [3:0] readys_unready = _GEN_19 | _readys_unready_T_4; // @[Arbiter.scala 25:58]
  wire [1:0] _readys_readys_T_2 = readys_unready[3:2] & readys_unready[1:0]; // @[Arbiter.scala 26:39]
  wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
  wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[1:0]; // @[package.scala 244:43]
  wire  readys__0 = readys_readys[0]; // @[Xbar.scala 255:69]
  wire  readys__1 = readys_readys[1]; // @[Xbar.scala 255:69]
  wire  winner__0 = readys__0 & auto_in_0_ar_valid; // @[Xbar.scala 257:63]
  wire  winner__1 = readys__1 & auto_in_1_ar_valid; // @[Xbar.scala 257:63]
  reg  state__0; // @[Xbar.scala 268:24]
  reg  state__1; // @[Xbar.scala 268:24]
  wire  muxState__0 = idle ? winner__0 : state__0; // @[Xbar.scala 269:23]
  wire  muxState__1 = idle ? winner__1 : state__1; // @[Xbar.scala 269:23]
  wire  _GEN_6 = anyValid ? 1'h0 : idle; // @[Xbar.scala 273:21 249:23 273:28]
  wire  _out_0_ar_valid_T_2 = state__0 & auto_in_0_ar_valid | state__1 & auto_in_1_ar_valid; // @[Mux.scala 27:73]
  wire  out_0_ar_valid = idle ? anyValid : _out_0_ar_valid_T_2; // @[Xbar.scala 285:22]
  wire  _T_18 = auto_out_ar_ready & out_0_ar_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_7 = _T_18 | _GEN_6; // @[Xbar.scala 274:{24,31}]
  wire  allowed_0 = idle ? readys__0 : state__0; // @[Xbar.scala 277:24]
  wire  allowed_1 = idle ? readys__1 : state__1; // @[Xbar.scala 277:24]
  wire [1:0] _T_19 = muxState__0 ? auto_in_0_ar_bits_echo_tl_state_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_20 = muxState__1 ? auto_in_1_ar_bits_echo_tl_state_source : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_22 = muxState__0 ? auto_in_0_ar_bits_echo_tl_state_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_23 = muxState__1 ? auto_in_1_ar_bits_echo_tl_state_size : 4'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_37 = muxState__0 ? auto_in_0_ar_bits_burst : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_38 = muxState__1 ? auto_in_1_ar_bits_burst : 2'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_40 = muxState__0 ? auto_in_0_ar_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_41 = muxState__1 ? auto_in_1_ar_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_43 = muxState__0 ? auto_in_0_ar_bits_len : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _T_44 = muxState__1 ? auto_in_1_ar_bits_len : 8'h0; // @[Mux.scala 27:73]
  wire [11:0] _T_46 = muxState__0 ? auto_in_0_ar_bits_addr : 12'h0; // @[Mux.scala 27:73]
  wire [11:0] _T_47 = muxState__1 ? auto_in_1_ar_bits_addr : 12'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_60 = awOut_0_io_deq_bits[0] ? auto_in_0_w_bits_strb : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_61 = awOut_0_io_deq_bits[1] ? auto_in_1_w_bits_strb : 4'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_63 = awOut_0_io_deq_bits[0] ? auto_in_0_w_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_64 = awOut_0_io_deq_bits[1] ? auto_in_1_w_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire  _T_67 = ~portsRIO_filtered_0_valid; // @[Xbar.scala 263:60]
  wire  _T_79 = ~portsBIO_filtered_0_valid; // @[Xbar.scala 263:60]
  wire  _T_91 = ~portsRIO_filtered_1_valid; // @[Xbar.scala 263:60]
  wire  _T_103 = ~portsBIO_filtered_1_valid; // @[Xbar.scala 263:60]
  QueueCompatibility_2 awOut_0 ( // @[Xbar.scala 63:47]
    .clock(awOut_0_clock),
    .reset(awOut_0_reset),
    .io_enq_ready(awOut_0_io_enq_ready),
    .io_enq_valid(awOut_0_io_enq_valid),
    .io_enq_bits(awOut_0_io_enq_bits),
    .io_deq_ready(awOut_0_io_deq_ready),
    .io_deq_valid(awOut_0_io_deq_valid),
    .io_deq_bits(awOut_0_io_deq_bits)
  );
  assign auto_in_1_aw_ready = out_0_aw_ready & awOut_0_io_enq_bits_allowed_1; // @[Xbar.scala 279:31]
  assign auto_in_1_w_ready = out_0_w_ready & awOut_0_io_deq_bits[1]; // @[Xbar.scala 197:37]
  assign auto_in_1_b_valid = auto_out_b_valid & requestBOI_0_1; // @[Xbar.scala 229:40]
  assign auto_in_1_b_bits_resp = auto_out_b_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_ar_ready = auto_out_ar_ready & allowed_1; // @[Xbar.scala 279:31]
  assign auto_in_1_r_valid = auto_out_r_valid & requestROI_0_1; // @[Xbar.scala 229:40]
  assign auto_in_1_r_bits_data = auto_out_r_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_r_bits_resp = auto_out_r_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_r_bits_last = auto_out_r_bits_last; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_aw_ready = out_0_aw_ready & awOut_0_io_enq_bits_allowed_0; // @[Xbar.scala 279:31]
  assign auto_in_0_w_ready = out_0_w_ready & awOut_0_io_deq_bits[0]; // @[Xbar.scala 197:37]
  assign auto_in_0_b_valid = auto_out_b_valid & auto_out_b_bits_id; // @[Xbar.scala 229:40]
  assign auto_in_0_b_bits_resp = auto_out_b_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_ar_ready = auto_out_ar_ready & allowed_0; // @[Xbar.scala 279:31]
  assign auto_in_0_r_valid = auto_out_r_valid & auto_out_r_bits_id; // @[Xbar.scala 229:40]
  assign auto_in_0_r_bits_data = auto_out_r_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_r_bits_resp = auto_out_r_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_r_bits_last = auto_out_r_bits_last; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_aw_valid = out_0_aw_valid & (latched | awOut_0_io_enq_ready); // @[Xbar.scala 166:47]
  assign auto_out_aw_bits_id = awOut_0_io_enq_bits_muxState_0 | awOut_0_io_enq_bits_muxState_1 & auto_in_1_aw_bits_id; // @[Mux.scala 27:73]
  assign auto_out_aw_bits_addr = _awOut_0_io_enq_bits_T_44 | _awOut_0_io_enq_bits_T_45; // @[Mux.scala 27:73]
  assign auto_out_aw_bits_len = _awOut_0_io_enq_bits_T_41 | _awOut_0_io_enq_bits_T_42; // @[Mux.scala 27:73]
  assign auto_out_aw_bits_size = _awOut_0_io_enq_bits_T_38 | _awOut_0_io_enq_bits_T_39; // @[Mux.scala 27:73]
  assign auto_out_aw_bits_burst = _awOut_0_io_enq_bits_T_35 | _awOut_0_io_enq_bits_T_36; // @[Mux.scala 27:73]
  assign auto_out_aw_bits_echo_tl_state_size = _awOut_0_io_enq_bits_T_20 | _awOut_0_io_enq_bits_T_21; // @[Mux.scala 27:73]
  assign auto_out_aw_bits_echo_tl_state_source = _awOut_0_io_enq_bits_T_17 | _awOut_0_io_enq_bits_T_18; // @[Mux.scala 27:73]
  assign auto_out_w_valid = out_0_w_valid & awOut_0_io_deq_valid; // @[Xbar.scala 173:45]
  assign auto_out_w_bits_data = _T_63 | _T_64; // @[Mux.scala 27:73]
  assign auto_out_w_bits_strb = _T_60 | _T_61; // @[Mux.scala 27:73]
  assign auto_out_w_bits_last = awOut_0_io_deq_bits[0] & auto_in_0_w_bits_last | awOut_0_io_deq_bits[1] &
    auto_in_1_w_bits_last; // @[Mux.scala 27:73]
  assign auto_out_b_ready = auto_out_b_bits_id & auto_in_0_b_ready | requestBOI_0_1 & auto_in_1_b_ready; // @[Mux.scala 27:73]
  assign auto_out_ar_valid = idle ? anyValid : _out_0_ar_valid_T_2; // @[Xbar.scala 285:22]
  assign auto_out_ar_bits_id = muxState__0 | muxState__1 & auto_in_1_ar_bits_id; // @[Mux.scala 27:73]
  assign auto_out_ar_bits_addr = _T_46 | _T_47; // @[Mux.scala 27:73]
  assign auto_out_ar_bits_len = _T_43 | _T_44; // @[Mux.scala 27:73]
  assign auto_out_ar_bits_size = _T_40 | _T_41; // @[Mux.scala 27:73]
  assign auto_out_ar_bits_burst = _T_37 | _T_38; // @[Mux.scala 27:73]
  assign auto_out_ar_bits_echo_tl_state_size = _T_22 | _T_23; // @[Mux.scala 27:73]
  assign auto_out_ar_bits_echo_tl_state_source = _T_19 | _T_20; // @[Mux.scala 27:73]
  assign auto_out_r_ready = auto_out_r_bits_id & auto_in_0_r_ready | requestROI_0_1 & auto_in_1_r_ready; // @[Mux.scala 27:73]
  assign awOut_0_clock = clock;
  assign awOut_0_reset = reset;
  assign awOut_0_io_enq_valid = out_0_aw_valid & ~latched; // @[Xbar.scala 168:50]
  assign awOut_0_io_enq_bits = {awOut_0_io_enq_bits_muxState_1,awOut_0_io_enq_bits_muxState_0}; // @[Xbar.scala 190:81]
  assign awOut_0_io_deq_ready = out_0_w_valid & out_0_w_bits_last & auto_out_w_ready; // @[Xbar.scala 175:71]
  always @(posedge clock) begin
    if (reset) begin // @[Xbar.scala 165:30]
      latched <= 1'h0; // @[Xbar.scala 165:30]
    end else if (_T_1) begin // @[Xbar.scala 170:33]
      latched <= 1'h0; // @[Xbar.scala 170:43]
    end else begin
      latched <= _GEN_0;
    end
    awOut_0_io_enq_bits_idle <= reset | _GEN_4; // @[Xbar.scala 249:{23,23}]
    if (reset) begin // @[Xbar.scala 268:24]
      awOut_0_io_enq_bits_state_0 <= 1'h0; // @[Xbar.scala 268:24]
    end else if (awOut_0_io_enq_bits_idle) begin // @[Xbar.scala 269:23]
      awOut_0_io_enq_bits_state_0 <= awOut_0_io_enq_bits_winner_0;
    end
    if (reset) begin // @[Xbar.scala 268:24]
      awOut_0_io_enq_bits_state_1 <= 1'h0; // @[Xbar.scala 268:24]
    end else if (awOut_0_io_enq_bits_idle) begin // @[Xbar.scala 269:23]
      awOut_0_io_enq_bits_state_1 <= awOut_0_io_enq_bits_winner_1;
    end
    if (reset) begin // @[Arbiter.scala 23:23]
      awOut_0_io_enq_bits_readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
    end else if (awOut_0_io_enq_bits_idle & |awOut_0_io_enq_bits_readys_valid) begin // @[Arbiter.scala 27:32]
      awOut_0_io_enq_bits_readys_mask <= _awOut_0_io_enq_bits_readys_mask_T_3; // @[Arbiter.scala 28:12]
    end
    idle <= reset | _GEN_7; // @[Xbar.scala 249:{23,23}]
    if (reset) begin // @[Arbiter.scala 23:23]
      readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
    end else if (idle & |readys_valid) begin // @[Arbiter.scala 27:32]
      readys_mask <= _readys_mask_T_3; // @[Arbiter.scala 28:12]
    end
    if (reset) begin // @[Xbar.scala 268:24]
      state__0 <= 1'h0; // @[Xbar.scala 268:24]
    end else if (idle) begin // @[Xbar.scala 269:23]
      state__0 <= winner__0;
    end
    if (reset) begin // @[Xbar.scala 268:24]
      state__1 <= 1'h0; // @[Xbar.scala 268:24]
    end else if (idle) begin // @[Xbar.scala 269:23]
      state__1 <= winner__1;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_awOut_0_io_enq_bits_readys_T_3 & ~(~awOut_0_io_enq_bits_winner_0 | ~awOut_0_io_enq_bits_winner_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Xbar.scala:263 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Xbar.scala 263:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~awOut_0_io_enq_bits_winner_0 | ~awOut_0_io_enq_bits_winner_1) & _awOut_0_io_enq_bits_readys_T_3) begin
          $fatal; // @[Xbar.scala 263:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_awOut_0_io_enq_bits_readys_T_3 & ~(~awOut_0_io_enq_bits_anyValid | (awOut_0_io_enq_bits_winner_0 |
          awOut_0_io_enq_bits_winner_1))) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~awOut_0_io_enq_bits_anyValid | (awOut_0_io_enq_bits_winner_0 | awOut_0_io_enq_bits_winner_1)) &
          _awOut_0_io_enq_bits_readys_T_3) begin
          $fatal; // @[Xbar.scala 265:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_awOut_0_io_enq_bits_readys_T_3 & ~(~winner__0 | ~winner__1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Xbar.scala:263 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Xbar.scala 263:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~winner__0 | ~winner__1) & _awOut_0_io_enq_bits_readys_T_3) begin
          $fatal; // @[Xbar.scala 263:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_awOut_0_io_enq_bits_readys_T_3 & ~(~anyValid | (winner__0 | winner__1))) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~anyValid | (winner__0 | winner__1)) & _awOut_0_io_enq_bits_readys_T_3) begin
          $fatal; // @[Xbar.scala 265:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_awOut_0_io_enq_bits_readys_T_3 & ~(_T_67 | portsRIO_filtered_0_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_67 | portsRIO_filtered_0_valid) & _awOut_0_io_enq_bits_readys_T_3) begin
          $fatal; // @[Xbar.scala 265:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_awOut_0_io_enq_bits_readys_T_3 & ~(_T_79 | portsBIO_filtered_0_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_79 | portsBIO_filtered_0_valid) & _awOut_0_io_enq_bits_readys_T_3) begin
          $fatal; // @[Xbar.scala 265:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_awOut_0_io_enq_bits_readys_T_3 & ~(_T_91 | portsRIO_filtered_1_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_91 | portsRIO_filtered_1_valid) & _awOut_0_io_enq_bits_readys_T_3) begin
          $fatal; // @[Xbar.scala 265:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_awOut_0_io_enq_bits_readys_T_3 & ~(_T_103 | portsBIO_filtered_1_valid)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Xbar.scala:265 assert (!anyValid || winner.reduce(_||_))\n"); // @[Xbar.scala 265:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_103 | portsBIO_filtered_1_valid) & _awOut_0_io_enq_bits_readys_T_3) begin
          $fatal; // @[Xbar.scala 265:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  latched = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  awOut_0_io_enq_bits_idle = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  awOut_0_io_enq_bits_state_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  awOut_0_io_enq_bits_state_1 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  awOut_0_io_enq_bits_readys_mask = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  idle = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  readys_mask = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  state__0 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  state__1 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AXI4RAM(
  input         clock,
  input         reset,
  output        auto_in_aw_ready,
  input         auto_in_aw_valid,
  input         auto_in_aw_bits_id,
  input  [11:0] auto_in_aw_bits_addr,
  input  [3:0]  auto_in_aw_bits_echo_tl_state_size,
  input  [1:0]  auto_in_aw_bits_echo_tl_state_source,
  input         auto_in_aw_bits_echo_real_last,
  output        auto_in_w_ready,
  input         auto_in_w_valid,
  input  [31:0] auto_in_w_bits_data,
  input  [3:0]  auto_in_w_bits_strb,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output        auto_in_b_bits_id,
  output [1:0]  auto_in_b_bits_resp,
  output [3:0]  auto_in_b_bits_echo_tl_state_size,
  output [1:0]  auto_in_b_bits_echo_tl_state_source,
  output        auto_in_b_bits_echo_real_last,
  output        auto_in_ar_ready,
  input         auto_in_ar_valid,
  input         auto_in_ar_bits_id,
  input  [11:0] auto_in_ar_bits_addr,
  input  [3:0]  auto_in_ar_bits_echo_tl_state_size,
  input  [1:0]  auto_in_ar_bits_echo_tl_state_source,
  input         auto_in_ar_bits_echo_real_last,
  input         auto_in_r_ready,
  output        auto_in_r_valid,
  output        auto_in_r_bits_id,
  output [31:0] auto_in_r_bits_data,
  output [1:0]  auto_in_r_bits_resp,
  output [3:0]  auto_in_r_bits_echo_tl_state_size,
  output [1:0]  auto_in_r_bits_echo_tl_state_source,
  output        auto_in_r_bits_echo_real_last
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
`endif // RANDOMIZE_REG_INIT
  reg [7:0] mem_0 [0:1023]; // @[DescribedSRAM.scala 19:26]
  wire  mem_0_rdata_MPORT_en; // @[DescribedSRAM.scala 19:26]
  wire [9:0] mem_0_rdata_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire [7:0] mem_0_rdata_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [7:0] mem_0_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [9:0] mem_0_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire  mem_0_MPORT_mask; // @[DescribedSRAM.scala 19:26]
  wire  mem_0_MPORT_en; // @[DescribedSRAM.scala 19:26]
  reg  mem_0_rdata_MPORT_en_pipe_0;
  reg [9:0] mem_0_rdata_MPORT_addr_pipe_0;
  reg [7:0] mem_1 [0:1023]; // @[DescribedSRAM.scala 19:26]
  wire  mem_1_rdata_MPORT_en; // @[DescribedSRAM.scala 19:26]
  wire [9:0] mem_1_rdata_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire [7:0] mem_1_rdata_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [7:0] mem_1_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [9:0] mem_1_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire  mem_1_MPORT_mask; // @[DescribedSRAM.scala 19:26]
  wire  mem_1_MPORT_en; // @[DescribedSRAM.scala 19:26]
  reg  mem_1_rdata_MPORT_en_pipe_0;
  reg [9:0] mem_1_rdata_MPORT_addr_pipe_0;
  reg [7:0] mem_2 [0:1023]; // @[DescribedSRAM.scala 19:26]
  wire  mem_2_rdata_MPORT_en; // @[DescribedSRAM.scala 19:26]
  wire [9:0] mem_2_rdata_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire [7:0] mem_2_rdata_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [7:0] mem_2_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [9:0] mem_2_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire  mem_2_MPORT_mask; // @[DescribedSRAM.scala 19:26]
  wire  mem_2_MPORT_en; // @[DescribedSRAM.scala 19:26]
  reg  mem_2_rdata_MPORT_en_pipe_0;
  reg [9:0] mem_2_rdata_MPORT_addr_pipe_0;
  reg [7:0] mem_3 [0:1023]; // @[DescribedSRAM.scala 19:26]
  wire  mem_3_rdata_MPORT_en; // @[DescribedSRAM.scala 19:26]
  wire [9:0] mem_3_rdata_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire [7:0] mem_3_rdata_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [7:0] mem_3_MPORT_data; // @[DescribedSRAM.scala 19:26]
  wire [9:0] mem_3_MPORT_addr; // @[DescribedSRAM.scala 19:26]
  wire  mem_3_MPORT_mask; // @[DescribedSRAM.scala 19:26]
  wire  mem_3_MPORT_en; // @[DescribedSRAM.scala 19:26]
  reg  mem_3_rdata_MPORT_en_pipe_0;
  reg [9:0] mem_3_rdata_MPORT_addr_pipe_0;
  wire [4:0] r_addr_lo = {auto_in_ar_bits_addr[6],auto_in_ar_bits_addr[5],auto_in_ar_bits_addr[4],auto_in_ar_bits_addr[3
    ],auto_in_ar_bits_addr[2]}; // @[Cat.scala 33:92]
  wire [4:0] r_addr_hi = {auto_in_ar_bits_addr[11],auto_in_ar_bits_addr[10],auto_in_ar_bits_addr[9],auto_in_ar_bits_addr
    [8],auto_in_ar_bits_addr[7]}; // @[Cat.scala 33:92]
  wire [4:0] w_addr_lo = {auto_in_aw_bits_addr[6],auto_in_aw_bits_addr[5],auto_in_aw_bits_addr[4],auto_in_aw_bits_addr[3
    ],auto_in_aw_bits_addr[2]}; // @[Cat.scala 33:92]
  wire [4:0] w_addr_hi = {auto_in_aw_bits_addr[11],auto_in_aw_bits_addr[10],auto_in_aw_bits_addr[9],auto_in_aw_bits_addr
    [8],auto_in_aw_bits_addr[7]}; // @[Cat.scala 33:92]
  wire [12:0] _r_sel0_T_1 = {1'b0,$signed(auto_in_ar_bits_addr)}; // @[Parameters.scala 137:49]
  wire [12:0] _r_sel0_T_3 = $signed(_r_sel0_T_1) & 13'sh1000; // @[Parameters.scala 137:52]
  wire  r_sel0 = $signed(_r_sel0_T_3) == 13'sh0; // @[Parameters.scala 137:67]
  wire [12:0] _w_sel0_T_1 = {1'b0,$signed(auto_in_aw_bits_addr)}; // @[Parameters.scala 137:49]
  wire [12:0] _w_sel0_T_3 = $signed(_w_sel0_T_1) & 13'sh1000; // @[Parameters.scala 137:52]
  wire  w_sel0 = $signed(_w_sel0_T_3) == 13'sh0; // @[Parameters.scala 137:67]
  reg  w_full; // @[SRAM.scala 70:25]
  reg  w_id; // @[SRAM.scala 71:21]
  reg [3:0] w_echo_tl_state_size; // @[SRAM.scala 72:21]
  reg [1:0] w_echo_tl_state_source; // @[SRAM.scala 72:21]
  reg  w_echo_real_last; // @[SRAM.scala 72:21]
  reg  r_sel1; // @[SRAM.scala 73:21]
  reg  w_sel1; // @[SRAM.scala 74:21]
  wire  _T = auto_in_b_ready & w_full; // @[Decoupled.scala 52:35]
  wire  _GEN_0 = _T ? 1'h0 : w_full; // @[SRAM.scala 70:25 76:{25,34}]
  wire  _bundleIn_0_aw_ready_T_1 = auto_in_b_ready | ~w_full; // @[SRAM.scala 92:47]
  wire  in_aw_ready = auto_in_w_valid & (auto_in_b_ready | ~w_full); // @[SRAM.scala 92:32]
  wire  _T_1 = in_aw_ready & auto_in_aw_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_1 = _T_1 | _GEN_0; // @[SRAM.scala 77:{25,34}]
  reg  r_full; // @[SRAM.scala 99:25]
  reg  r_id; // @[SRAM.scala 100:21]
  reg [3:0] r_echo_tl_state_size; // @[SRAM.scala 101:21]
  reg [1:0] r_echo_tl_state_source; // @[SRAM.scala 101:21]
  reg  r_echo_real_last; // @[SRAM.scala 101:21]
  wire  _T_9 = auto_in_r_ready & r_full; // @[Decoupled.scala 52:35]
  wire  _GEN_26 = _T_9 ? 1'h0 : r_full; // @[SRAM.scala 103:{25,34} 99:25]
  wire  in_ar_ready = auto_in_r_ready | ~r_full; // @[SRAM.scala 117:31]
  wire  _T_10 = in_ar_ready & auto_in_ar_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_27 = _T_10 | _GEN_26; // @[SRAM.scala 104:{25,34}]
  reg  rdata_REG; // @[package.scala 91:91]
  reg [7:0] rdata_r_0; // @[Reg.scala 19:16]
  reg [7:0] rdata_r_1; // @[Reg.scala 19:16]
  reg [7:0] rdata_r_2; // @[Reg.scala 19:16]
  reg [7:0] rdata_r_3; // @[Reg.scala 19:16]
  wire [7:0] _GEN_37 = rdata_REG ? mem_0_rdata_MPORT_data : rdata_r_0; // @[Reg.scala 19:16 20:{18,22}]
  wire [7:0] _GEN_38 = rdata_REG ? mem_1_rdata_MPORT_data : rdata_r_1; // @[Reg.scala 19:16 20:{18,22}]
  wire [7:0] _GEN_39 = rdata_REG ? mem_2_rdata_MPORT_data : rdata_r_2; // @[Reg.scala 19:16 20:{18,22}]
  wire [7:0] _GEN_40 = rdata_REG ? mem_3_rdata_MPORT_data : rdata_r_3; // @[Reg.scala 19:16 20:{18,22}]
  wire [15:0] bundleIn_0_r_bits_data_lo = {_GEN_38,_GEN_37}; // @[Cat.scala 33:92]
  wire [15:0] bundleIn_0_r_bits_data_hi = {_GEN_40,_GEN_39}; // @[Cat.scala 33:92]
  assign mem_0_rdata_MPORT_en = mem_0_rdata_MPORT_en_pipe_0;
  assign mem_0_rdata_MPORT_addr = mem_0_rdata_MPORT_addr_pipe_0;
  assign mem_0_rdata_MPORT_data = mem_0[mem_0_rdata_MPORT_addr]; // @[DescribedSRAM.scala 19:26]
  assign mem_0_MPORT_data = auto_in_w_bits_data[7:0];
  assign mem_0_MPORT_addr = {w_addr_hi,w_addr_lo};
  assign mem_0_MPORT_mask = auto_in_w_bits_strb[0];
  assign mem_0_MPORT_en = _T_1 & w_sel0;
  assign mem_1_rdata_MPORT_en = mem_1_rdata_MPORT_en_pipe_0;
  assign mem_1_rdata_MPORT_addr = mem_1_rdata_MPORT_addr_pipe_0;
  assign mem_1_rdata_MPORT_data = mem_1[mem_1_rdata_MPORT_addr]; // @[DescribedSRAM.scala 19:26]
  assign mem_1_MPORT_data = auto_in_w_bits_data[15:8];
  assign mem_1_MPORT_addr = {w_addr_hi,w_addr_lo};
  assign mem_1_MPORT_mask = auto_in_w_bits_strb[1];
  assign mem_1_MPORT_en = _T_1 & w_sel0;
  assign mem_2_rdata_MPORT_en = mem_2_rdata_MPORT_en_pipe_0;
  assign mem_2_rdata_MPORT_addr = mem_2_rdata_MPORT_addr_pipe_0;
  assign mem_2_rdata_MPORT_data = mem_2[mem_2_rdata_MPORT_addr]; // @[DescribedSRAM.scala 19:26]
  assign mem_2_MPORT_data = auto_in_w_bits_data[23:16];
  assign mem_2_MPORT_addr = {w_addr_hi,w_addr_lo};
  assign mem_2_MPORT_mask = auto_in_w_bits_strb[2];
  assign mem_2_MPORT_en = _T_1 & w_sel0;
  assign mem_3_rdata_MPORT_en = mem_3_rdata_MPORT_en_pipe_0;
  assign mem_3_rdata_MPORT_addr = mem_3_rdata_MPORT_addr_pipe_0;
  assign mem_3_rdata_MPORT_data = mem_3[mem_3_rdata_MPORT_addr]; // @[DescribedSRAM.scala 19:26]
  assign mem_3_MPORT_data = auto_in_w_bits_data[31:24];
  assign mem_3_MPORT_addr = {w_addr_hi,w_addr_lo};
  assign mem_3_MPORT_mask = auto_in_w_bits_strb[3];
  assign mem_3_MPORT_en = _T_1 & w_sel0;
  assign auto_in_aw_ready = auto_in_w_valid & (auto_in_b_ready | ~w_full); // @[SRAM.scala 92:32]
  assign auto_in_w_ready = auto_in_aw_valid & _bundleIn_0_aw_ready_T_1; // @[SRAM.scala 93:32]
  assign auto_in_b_valid = w_full; // @[Nodes.scala 1210:84 SRAM.scala 91:17]
  assign auto_in_b_bits_id = w_id; // @[Nodes.scala 1210:84 SRAM.scala 95:20]
  assign auto_in_b_bits_resp = w_sel1 ? 2'h0 : 2'h3; // @[SRAM.scala 96:26]
  assign auto_in_b_bits_echo_tl_state_size = w_echo_tl_state_size; // @[Nodes.scala 1210:84 BundleMap.scala 247:19]
  assign auto_in_b_bits_echo_tl_state_source = w_echo_tl_state_source; // @[Nodes.scala 1210:84 BundleMap.scala 247:19]
  assign auto_in_b_bits_echo_real_last = w_echo_real_last; // @[Nodes.scala 1210:84 BundleMap.scala 247:19]
  assign auto_in_ar_ready = auto_in_r_ready | ~r_full; // @[SRAM.scala 117:31]
  assign auto_in_r_valid = r_full; // @[Nodes.scala 1210:84 SRAM.scala 116:17]
  assign auto_in_r_bits_id = r_id; // @[Nodes.scala 1210:84 SRAM.scala 119:20]
  assign auto_in_r_bits_data = {bundleIn_0_r_bits_data_hi,bundleIn_0_r_bits_data_lo}; // @[Cat.scala 33:92]
  assign auto_in_r_bits_resp = r_sel1 ? 2'h0 : 2'h3; // @[SRAM.scala 120:26]
  assign auto_in_r_bits_echo_tl_state_size = r_echo_tl_state_size; // @[Nodes.scala 1210:84 BundleMap.scala 247:19]
  assign auto_in_r_bits_echo_tl_state_source = r_echo_tl_state_source; // @[Nodes.scala 1210:84 BundleMap.scala 247:19]
  assign auto_in_r_bits_echo_real_last = r_echo_real_last; // @[Nodes.scala 1210:84 BundleMap.scala 247:19]
  always @(posedge clock) begin
    if (mem_0_MPORT_en & mem_0_MPORT_mask) begin
      mem_0[mem_0_MPORT_addr] <= mem_0_MPORT_data; // @[DescribedSRAM.scala 19:26]
    end
    mem_0_rdata_MPORT_en_pipe_0 <= in_ar_ready & auto_in_ar_valid;
    if (in_ar_ready & auto_in_ar_valid) begin
      mem_0_rdata_MPORT_addr_pipe_0 <= {r_addr_hi,r_addr_lo};
    end
    if (mem_1_MPORT_en & mem_1_MPORT_mask) begin
      mem_1[mem_1_MPORT_addr] <= mem_1_MPORT_data; // @[DescribedSRAM.scala 19:26]
    end
    mem_1_rdata_MPORT_en_pipe_0 <= in_ar_ready & auto_in_ar_valid;
    if (in_ar_ready & auto_in_ar_valid) begin
      mem_1_rdata_MPORT_addr_pipe_0 <= {r_addr_hi,r_addr_lo};
    end
    if (mem_2_MPORT_en & mem_2_MPORT_mask) begin
      mem_2[mem_2_MPORT_addr] <= mem_2_MPORT_data; // @[DescribedSRAM.scala 19:26]
    end
    mem_2_rdata_MPORT_en_pipe_0 <= in_ar_ready & auto_in_ar_valid;
    if (in_ar_ready & auto_in_ar_valid) begin
      mem_2_rdata_MPORT_addr_pipe_0 <= {r_addr_hi,r_addr_lo};
    end
    if (mem_3_MPORT_en & mem_3_MPORT_mask) begin
      mem_3[mem_3_MPORT_addr] <= mem_3_MPORT_data; // @[DescribedSRAM.scala 19:26]
    end
    mem_3_rdata_MPORT_en_pipe_0 <= in_ar_ready & auto_in_ar_valid;
    if (in_ar_ready & auto_in_ar_valid) begin
      mem_3_rdata_MPORT_addr_pipe_0 <= {r_addr_hi,r_addr_lo};
    end
    if (reset) begin // @[SRAM.scala 70:25]
      w_full <= 1'h0; // @[SRAM.scala 70:25]
    end else begin
      w_full <= _GEN_1;
    end
    if (_T_1) begin // @[SRAM.scala 79:25]
      w_id <= auto_in_aw_bits_id; // @[SRAM.scala 80:12]
    end
    if (_T_1) begin // @[SRAM.scala 79:25]
      w_echo_tl_state_size <= auto_in_aw_bits_echo_tl_state_size; // @[BundleMap.scala 247:19]
    end
    if (_T_1) begin // @[SRAM.scala 79:25]
      w_echo_tl_state_source <= auto_in_aw_bits_echo_tl_state_source; // @[BundleMap.scala 247:19]
    end
    if (_T_1) begin // @[SRAM.scala 79:25]
      w_echo_real_last <= auto_in_aw_bits_echo_real_last; // @[BundleMap.scala 247:19]
    end
    if (_T_10) begin // @[SRAM.scala 106:25]
      r_sel1 <= r_sel0; // @[SRAM.scala 108:14]
    end
    if (_T_1) begin // @[SRAM.scala 79:25]
      w_sel1 <= w_sel0; // @[SRAM.scala 81:14]
    end
    if (reset) begin // @[SRAM.scala 99:25]
      r_full <= 1'h0; // @[SRAM.scala 99:25]
    end else begin
      r_full <= _GEN_27;
    end
    if (_T_10) begin // @[SRAM.scala 106:25]
      r_id <= auto_in_ar_bits_id; // @[SRAM.scala 107:12]
    end
    if (_T_10) begin // @[SRAM.scala 106:25]
      r_echo_tl_state_size <= auto_in_ar_bits_echo_tl_state_size; // @[BundleMap.scala 247:19]
    end
    if (_T_10) begin // @[SRAM.scala 106:25]
      r_echo_tl_state_source <= auto_in_ar_bits_echo_tl_state_source; // @[BundleMap.scala 247:19]
    end
    if (_T_10) begin // @[SRAM.scala 106:25]
      r_echo_real_last <= auto_in_ar_bits_echo_real_last; // @[BundleMap.scala 247:19]
    end
    rdata_REG <= in_ar_ready & auto_in_ar_valid; // @[Decoupled.scala 52:35]
    if (rdata_REG) begin // @[Reg.scala 20:18]
      rdata_r_0 <= mem_0_rdata_MPORT_data; // @[Reg.scala 20:22]
    end
    if (rdata_REG) begin // @[Reg.scala 20:18]
      rdata_r_1 <= mem_1_rdata_MPORT_data; // @[Reg.scala 20:22]
    end
    if (rdata_REG) begin // @[Reg.scala 20:18]
      rdata_r_2 <= mem_2_rdata_MPORT_data; // @[Reg.scala 20:22]
    end
    if (rdata_REG) begin // @[Reg.scala 20:18]
      rdata_r_3 <= mem_3_rdata_MPORT_data; // @[Reg.scala 20:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    mem_0[initvar] = _RAND_0[7:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    mem_1[initvar] = _RAND_3[7:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    mem_2[initvar] = _RAND_6[7:0];
  _RAND_9 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    mem_3[initvar] = _RAND_9[7:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  mem_0_rdata_MPORT_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  mem_0_rdata_MPORT_addr_pipe_0 = _RAND_2[9:0];
  _RAND_4 = {1{`RANDOM}};
  mem_1_rdata_MPORT_en_pipe_0 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  mem_1_rdata_MPORT_addr_pipe_0 = _RAND_5[9:0];
  _RAND_7 = {1{`RANDOM}};
  mem_2_rdata_MPORT_en_pipe_0 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  mem_2_rdata_MPORT_addr_pipe_0 = _RAND_8[9:0];
  _RAND_10 = {1{`RANDOM}};
  mem_3_rdata_MPORT_en_pipe_0 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  mem_3_rdata_MPORT_addr_pipe_0 = _RAND_11[9:0];
  _RAND_12 = {1{`RANDOM}};
  w_full = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  w_id = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  w_echo_tl_state_size = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  w_echo_tl_state_source = _RAND_15[1:0];
  _RAND_16 = {1{`RANDOM}};
  w_echo_real_last = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  r_sel1 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  w_sel1 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  r_full = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  r_id = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  r_echo_tl_state_size = _RAND_21[3:0];
  _RAND_22 = {1{`RANDOM}};
  r_echo_tl_state_source = _RAND_22[1:0];
  _RAND_23 = {1{`RANDOM}};
  r_echo_real_last = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  rdata_REG = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  rdata_r_0 = _RAND_25[7:0];
  _RAND_26 = {1{`RANDOM}};
  rdata_r_1 = _RAND_26[7:0];
  _RAND_27 = {1{`RANDOM}};
  rdata_r_2 = _RAND_27[7:0];
  _RAND_28 = {1{`RANDOM}};
  rdata_r_3 = _RAND_28[7:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_id,
  input  [11:0] io_enq_bits_addr,
  input  [7:0]  io_enq_bits_len,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_burst,
  input  [3:0]  io_enq_bits_echo_tl_state_size,
  input  [1:0]  io_enq_bits_echo_tl_state_source,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_id,
  output [11:0] io_deq_bits_addr,
  output [7:0]  io_deq_bits_len,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_burst,
  output [3:0]  io_deq_bits_echo_tl_state_size,
  output [1:0]  io_deq_bits_echo_tl_state_source
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  ram_id [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_en; // @[Decoupled.scala 275:95]
  reg [11:0] ram_addr [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_addr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_addr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [11:0] ram_addr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [11:0] ram_addr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_addr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_addr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_addr_MPORT_en; // @[Decoupled.scala 275:95]
  reg [7:0] ram_len [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_len_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_len_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [7:0] ram_len_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [7:0] ram_len_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_len_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_len_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_len_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_burst [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_burst_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_burst_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_burst_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_burst_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_burst_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_burst_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_burst_MPORT_en; // @[Decoupled.scala 275:95]
  reg [3:0] ram_echo_tl_state_size [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_echo_tl_state_source [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_19 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_19 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_id_io_deq_bits_MPORT_en = 1'h1;
  assign ram_id_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_id_io_deq_bits_MPORT_data = ram_id[ram_id_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_id_MPORT_data = io_enq_bits_id;
  assign ram_id_MPORT_addr = 1'h0;
  assign ram_id_MPORT_mask = 1'h1;
  assign ram_id_MPORT_en = empty ? _GEN_19 : _do_enq_T;
  assign ram_addr_io_deq_bits_MPORT_en = 1'h1;
  assign ram_addr_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_addr_io_deq_bits_MPORT_data = ram_addr[ram_addr_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_addr_MPORT_data = io_enq_bits_addr;
  assign ram_addr_MPORT_addr = 1'h0;
  assign ram_addr_MPORT_mask = 1'h1;
  assign ram_addr_MPORT_en = empty ? _GEN_19 : _do_enq_T;
  assign ram_len_io_deq_bits_MPORT_en = 1'h1;
  assign ram_len_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_len_io_deq_bits_MPORT_data = ram_len[ram_len_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_len_MPORT_data = io_enq_bits_len;
  assign ram_len_MPORT_addr = 1'h0;
  assign ram_len_MPORT_mask = 1'h1;
  assign ram_len_MPORT_en = empty ? _GEN_19 : _do_enq_T;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = 1'h0;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = empty ? _GEN_19 : _do_enq_T;
  assign ram_burst_io_deq_bits_MPORT_en = 1'h1;
  assign ram_burst_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_burst_io_deq_bits_MPORT_data = ram_burst[ram_burst_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_burst_MPORT_data = io_enq_bits_burst;
  assign ram_burst_MPORT_addr = 1'h0;
  assign ram_burst_MPORT_mask = 1'h1;
  assign ram_burst_MPORT_en = empty ? _GEN_19 : _do_enq_T;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_data =
    ram_echo_tl_state_size[ram_echo_tl_state_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_size_MPORT_data = io_enq_bits_echo_tl_state_size;
  assign ram_echo_tl_state_size_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_size_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_size_MPORT_en = empty ? _GEN_19 : _do_enq_T;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_data =
    ram_echo_tl_state_source[ram_echo_tl_state_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_source_MPORT_data = io_enq_bits_echo_tl_state_source;
  assign ram_echo_tl_state_source_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_source_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_source_MPORT_en = empty ? _GEN_19 : _do_enq_T;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_id = empty ? io_enq_bits_id : ram_id_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_addr = empty ? io_enq_bits_addr : ram_addr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_len = empty ? io_enq_bits_len : ram_len_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_size = empty ? io_enq_bits_size : ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_burst = empty ? io_enq_bits_burst : ram_burst_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_echo_tl_state_size = empty ? io_enq_bits_echo_tl_state_size :
    ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_echo_tl_state_source = empty ? io_enq_bits_echo_tl_state_source :
    ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_id_MPORT_en & ram_id_MPORT_mask) begin
      ram_id[ram_id_MPORT_addr] <= ram_id_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_addr_MPORT_en & ram_addr_MPORT_mask) begin
      ram_addr[ram_addr_MPORT_addr] <= ram_addr_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_len_MPORT_en & ram_len_MPORT_mask) begin
      ram_len[ram_len_MPORT_addr] <= ram_len_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_burst_MPORT_en & ram_burst_MPORT_mask) begin
      ram_burst[ram_burst_MPORT_addr] <= ram_burst_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_size_MPORT_en & ram_echo_tl_state_size_MPORT_mask) begin
      ram_echo_tl_state_size[ram_echo_tl_state_size_MPORT_addr] <= ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_source_MPORT_en & ram_echo_tl_state_source_MPORT_mask) begin
      ram_echo_tl_state_source[ram_echo_tl_state_source_MPORT_addr] <= ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_id[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_addr[initvar] = _RAND_1[11:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_len[initvar] = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_size[initvar] = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_burst[initvar] = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_echo_tl_state_size[initvar] = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_echo_tl_state_source[initvar] = _RAND_6[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  maybe_full = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_2(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [31:0] io_enq_bits_data,
  input  [3:0]  io_enq_bits_strb,
  input         io_enq_bits_last,
  input         io_deq_ready,
  output        io_deq_valid,
  output [31:0] io_deq_bits_data,
  output [3:0]  io_deq_bits_strb,
  output        io_deq_bits_last
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] ram_data [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg [3:0] ram_strb [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_strb_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_strb_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [3:0] ram_strb_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [3:0] ram_strb_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_strb_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_strb_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_strb_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_last [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_last_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_last_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_last_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_12 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_12 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = 1'h0;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = empty ? _GEN_12 : _do_enq_T;
  assign ram_strb_io_deq_bits_MPORT_en = 1'h1;
  assign ram_strb_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_strb_io_deq_bits_MPORT_data = ram_strb[ram_strb_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_strb_MPORT_data = io_enq_bits_strb;
  assign ram_strb_MPORT_addr = 1'h0;
  assign ram_strb_MPORT_mask = 1'h1;
  assign ram_strb_MPORT_en = empty ? _GEN_12 : _do_enq_T;
  assign ram_last_io_deq_bits_MPORT_en = 1'h1;
  assign ram_last_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_last_io_deq_bits_MPORT_data = ram_last[ram_last_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_last_MPORT_data = io_enq_bits_last;
  assign ram_last_MPORT_addr = 1'h0;
  assign ram_last_MPORT_mask = 1'h1;
  assign ram_last_MPORT_en = empty ? _GEN_12 : _do_enq_T;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_data = empty ? io_enq_bits_data : ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_strb = empty ? io_enq_bits_strb : ram_strb_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_last = empty ? io_enq_bits_last : ram_last_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_strb_MPORT_en & ram_strb_MPORT_mask) begin
      ram_strb[ram_strb_MPORT_addr] <= ram_strb_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_last_MPORT_en & ram_last_MPORT_mask) begin
      ram_last[ram_last_MPORT_addr] <= ram_last_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_data[initvar] = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_strb[initvar] = _RAND_1[3:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_last[initvar] = _RAND_2[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AXI4Fragmenter(
  input         clock,
  input         reset,
  output        auto_in_aw_ready,
  input         auto_in_aw_valid,
  input         auto_in_aw_bits_id,
  input  [11:0] auto_in_aw_bits_addr,
  input  [7:0]  auto_in_aw_bits_len,
  input  [2:0]  auto_in_aw_bits_size,
  input  [1:0]  auto_in_aw_bits_burst,
  input  [3:0]  auto_in_aw_bits_echo_tl_state_size,
  input  [1:0]  auto_in_aw_bits_echo_tl_state_source,
  output        auto_in_w_ready,
  input         auto_in_w_valid,
  input  [31:0] auto_in_w_bits_data,
  input  [3:0]  auto_in_w_bits_strb,
  input         auto_in_w_bits_last,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output        auto_in_b_bits_id,
  output [1:0]  auto_in_b_bits_resp,
  output [3:0]  auto_in_b_bits_echo_tl_state_size,
  output [1:0]  auto_in_b_bits_echo_tl_state_source,
  output        auto_in_ar_ready,
  input         auto_in_ar_valid,
  input         auto_in_ar_bits_id,
  input  [11:0] auto_in_ar_bits_addr,
  input  [7:0]  auto_in_ar_bits_len,
  input  [2:0]  auto_in_ar_bits_size,
  input  [1:0]  auto_in_ar_bits_burst,
  input  [3:0]  auto_in_ar_bits_echo_tl_state_size,
  input  [1:0]  auto_in_ar_bits_echo_tl_state_source,
  input         auto_in_r_ready,
  output        auto_in_r_valid,
  output        auto_in_r_bits_id,
  output [31:0] auto_in_r_bits_data,
  output [1:0]  auto_in_r_bits_resp,
  output [3:0]  auto_in_r_bits_echo_tl_state_size,
  output [1:0]  auto_in_r_bits_echo_tl_state_source,
  output        auto_in_r_bits_last,
  input         auto_out_aw_ready,
  output        auto_out_aw_valid,
  output        auto_out_aw_bits_id,
  output [11:0] auto_out_aw_bits_addr,
  output [3:0]  auto_out_aw_bits_echo_tl_state_size,
  output [1:0]  auto_out_aw_bits_echo_tl_state_source,
  output        auto_out_aw_bits_echo_real_last,
  input         auto_out_w_ready,
  output        auto_out_w_valid,
  output [31:0] auto_out_w_bits_data,
  output [3:0]  auto_out_w_bits_strb,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input         auto_out_b_bits_id,
  input  [1:0]  auto_out_b_bits_resp,
  input  [3:0]  auto_out_b_bits_echo_tl_state_size,
  input  [1:0]  auto_out_b_bits_echo_tl_state_source,
  input         auto_out_b_bits_echo_real_last,
  input         auto_out_ar_ready,
  output        auto_out_ar_valid,
  output        auto_out_ar_bits_id,
  output [11:0] auto_out_ar_bits_addr,
  output [3:0]  auto_out_ar_bits_echo_tl_state_size,
  output [1:0]  auto_out_ar_bits_echo_tl_state_source,
  output        auto_out_ar_bits_echo_real_last,
  output        auto_out_r_ready,
  input         auto_out_r_valid,
  input         auto_out_r_bits_id,
  input  [31:0] auto_out_r_bits_data,
  input  [1:0]  auto_out_r_bits_resp,
  input  [3:0]  auto_out_r_bits_echo_tl_state_size,
  input  [1:0]  auto_out_r_bits_echo_tl_state_source,
  input         auto_out_r_bits_echo_real_last
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  wire  deq_clock; // @[Decoupled.scala 377:21]
  wire  deq_reset; // @[Decoupled.scala 377:21]
  wire  deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire  deq_io_enq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] deq_io_enq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] deq_io_enq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] deq_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] deq_io_enq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] deq_io_enq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] deq_io_enq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire  deq_io_deq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] deq_io_deq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] deq_io_deq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] deq_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] deq_io_deq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  deq_1_clock; // @[Decoupled.scala 377:21]
  wire  deq_1_reset; // @[Decoupled.scala 377:21]
  wire  deq_1_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  deq_1_io_enq_valid; // @[Decoupled.scala 377:21]
  wire  deq_1_io_enq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] deq_1_io_enq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] deq_1_io_enq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] deq_1_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] deq_1_io_enq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] deq_1_io_enq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] deq_1_io_enq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  deq_1_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  deq_1_io_deq_valid; // @[Decoupled.scala 377:21]
  wire  deq_1_io_deq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] deq_1_io_deq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] deq_1_io_deq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] deq_1_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] deq_1_io_deq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] deq_1_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] deq_1_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  in_w_deq_clock; // @[Decoupled.scala 377:21]
  wire  in_w_deq_reset; // @[Decoupled.scala 377:21]
  wire  in_w_deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  in_w_deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [31:0] in_w_deq_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire [3:0] in_w_deq_io_enq_bits_strb; // @[Decoupled.scala 377:21]
  wire  in_w_deq_io_enq_bits_last; // @[Decoupled.scala 377:21]
  wire  in_w_deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  in_w_deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [31:0] in_w_deq_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire [3:0] in_w_deq_io_deq_bits_strb; // @[Decoupled.scala 377:21]
  wire  in_w_deq_io_deq_bits_last; // @[Decoupled.scala 377:21]
  reg  busy; // @[Fragmenter.scala 60:29]
  reg [11:0] r_addr; // @[Fragmenter.scala 61:25]
  reg [7:0] r_len; // @[Fragmenter.scala 62:25]
  wire [7:0] irr_bits_len = deq_io_deq_bits_len; // @[Decoupled.scala 417:19 418:14]
  wire [7:0] len = busy ? r_len : irr_bits_len; // @[Fragmenter.scala 64:23]
  wire [11:0] irr_bits_addr = deq_io_deq_bits_addr; // @[Decoupled.scala 417:19 418:14]
  wire [11:0] addr = busy ? r_addr : irr_bits_addr; // @[Fragmenter.scala 65:23]
  wire [1:0] irr_bits_burst = deq_io_deq_bits_burst; // @[Decoupled.scala 417:19 418:14]
  wire  fixed = irr_bits_burst == 2'h0; // @[Fragmenter.scala 92:34]
  wire [2:0] irr_bits_size = deq_io_deq_bits_size; // @[Decoupled.scala 417:19 418:14]
  wire [15:0] _inc_addr_T = 16'h1 << irr_bits_size; // @[Fragmenter.scala 100:38]
  wire [15:0] _GEN_20 = {{4'd0}, addr}; // @[Fragmenter.scala 100:29]
  wire [15:0] inc_addr = _GEN_20 + _inc_addr_T; // @[Fragmenter.scala 100:29]
  wire [15:0] _wrapMask_T = {irr_bits_len,8'hff}; // @[Cat.scala 33:92]
  wire [22:0] _GEN_39 = {{7'd0}, _wrapMask_T}; // @[Bundles.scala 31:21]
  wire [22:0] _wrapMask_T_1 = _GEN_39 << irr_bits_size; // @[Bundles.scala 31:21]
  wire [14:0] wrapMask = _wrapMask_T_1[22:8]; // @[Bundles.scala 31:30]
  wire [15:0] _GEN_21 = {{1'd0}, wrapMask}; // @[Fragmenter.scala 104:33]
  wire [15:0] _mux_addr_T = inc_addr & _GEN_21; // @[Fragmenter.scala 104:33]
  wire [11:0] _mux_addr_T_1 = ~irr_bits_addr; // @[Fragmenter.scala 104:49]
  wire [14:0] _GEN_22 = {{3'd0}, _mux_addr_T_1}; // @[Fragmenter.scala 104:62]
  wire [14:0] _mux_addr_T_2 = _GEN_22 | wrapMask; // @[Fragmenter.scala 104:62]
  wire [14:0] _mux_addr_T_3 = ~_mux_addr_T_2; // @[Fragmenter.scala 104:47]
  wire [15:0] _GEN_23 = {{1'd0}, _mux_addr_T_3}; // @[Fragmenter.scala 104:45]
  wire [15:0] _mux_addr_T_4 = _mux_addr_T | _GEN_23; // @[Fragmenter.scala 104:45]
  wire [15:0] _GEN_0 = irr_bits_burst == 2'h2 ? _mux_addr_T_4 : inc_addr; // @[Fragmenter.scala 103:59 104:20]
  wire [15:0] mux_addr = fixed ? {{4'd0}, irr_bits_addr} : _GEN_0; // @[Fragmenter.scala 106:60 107:20]
  wire  ar_last = 8'h0 == len; // @[Fragmenter.scala 110:27]
  wire [11:0] _out_bits_addr_T = ~addr; // @[Fragmenter.scala 122:28]
  wire [8:0] _out_bits_addr_T_2 = 9'h3 << irr_bits_size; // @[package.scala 234:77]
  wire [1:0] _out_bits_addr_T_4 = ~_out_bits_addr_T_2[1:0]; // @[package.scala 234:46]
  wire [11:0] _GEN_24 = {{10'd0}, _out_bits_addr_T_4}; // @[Fragmenter.scala 122:34]
  wire [11:0] _out_bits_addr_T_5 = _out_bits_addr_T | _GEN_24; // @[Fragmenter.scala 122:34]
  wire  irr_valid = deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  wire  _T_2 = auto_out_ar_ready & irr_valid; // @[Decoupled.scala 52:35]
  wire [8:0] _GEN_25 = {{1'd0}, len}; // @[Fragmenter.scala 127:25]
  wire [8:0] _r_len_T_1 = _GEN_25 - 9'h1; // @[Fragmenter.scala 127:25]
  wire [15:0] _GEN_3 = _T_2 ? mux_addr : {{4'd0}, r_addr}; // @[Fragmenter.scala 124:27 126:18 61:25]
  wire [8:0] _GEN_4 = _T_2 ? _r_len_T_1 : {{1'd0}, r_len}; // @[Fragmenter.scala 124:27 127:18 62:25]
  reg  busy_1; // @[Fragmenter.scala 60:29]
  reg [11:0] r_addr_1; // @[Fragmenter.scala 61:25]
  reg [7:0] r_len_1; // @[Fragmenter.scala 62:25]
  wire [7:0] irr_1_bits_len = deq_1_io_deq_bits_len; // @[Decoupled.scala 417:19 418:14]
  wire [7:0] len_1 = busy_1 ? r_len_1 : irr_1_bits_len; // @[Fragmenter.scala 64:23]
  wire [11:0] irr_1_bits_addr = deq_1_io_deq_bits_addr; // @[Decoupled.scala 417:19 418:14]
  wire [11:0] addr_1 = busy_1 ? r_addr_1 : irr_1_bits_addr; // @[Fragmenter.scala 65:23]
  wire [1:0] irr_1_bits_burst = deq_1_io_deq_bits_burst; // @[Decoupled.scala 417:19 418:14]
  wire  fixed_1 = irr_1_bits_burst == 2'h0; // @[Fragmenter.scala 92:34]
  wire [2:0] irr_1_bits_size = deq_1_io_deq_bits_size; // @[Decoupled.scala 417:19 418:14]
  wire [15:0] _inc_addr_T_2 = 16'h1 << irr_1_bits_size; // @[Fragmenter.scala 100:38]
  wire [15:0] _GEN_30 = {{4'd0}, addr_1}; // @[Fragmenter.scala 100:29]
  wire [15:0] inc_addr_1 = _GEN_30 + _inc_addr_T_2; // @[Fragmenter.scala 100:29]
  wire [15:0] _wrapMask_T_2 = {irr_1_bits_len,8'hff}; // @[Cat.scala 33:92]
  wire [22:0] _GEN_40 = {{7'd0}, _wrapMask_T_2}; // @[Bundles.scala 31:21]
  wire [22:0] _wrapMask_T_3 = _GEN_40 << irr_1_bits_size; // @[Bundles.scala 31:21]
  wire [14:0] wrapMask_1 = _wrapMask_T_3[22:8]; // @[Bundles.scala 31:30]
  wire [15:0] _GEN_31 = {{1'd0}, wrapMask_1}; // @[Fragmenter.scala 104:33]
  wire [15:0] _mux_addr_T_5 = inc_addr_1 & _GEN_31; // @[Fragmenter.scala 104:33]
  wire [11:0] _mux_addr_T_6 = ~irr_1_bits_addr; // @[Fragmenter.scala 104:49]
  wire [14:0] _GEN_32 = {{3'd0}, _mux_addr_T_6}; // @[Fragmenter.scala 104:62]
  wire [14:0] _mux_addr_T_7 = _GEN_32 | wrapMask_1; // @[Fragmenter.scala 104:62]
  wire [14:0] _mux_addr_T_8 = ~_mux_addr_T_7; // @[Fragmenter.scala 104:47]
  wire [15:0] _GEN_33 = {{1'd0}, _mux_addr_T_8}; // @[Fragmenter.scala 104:45]
  wire [15:0] _mux_addr_T_9 = _mux_addr_T_5 | _GEN_33; // @[Fragmenter.scala 104:45]
  wire [15:0] _GEN_5 = irr_1_bits_burst == 2'h2 ? _mux_addr_T_9 : inc_addr_1; // @[Fragmenter.scala 103:59 104:20]
  wire [15:0] mux_addr_1 = fixed_1 ? {{4'd0}, irr_1_bits_addr} : _GEN_5; // @[Fragmenter.scala 106:60 107:20]
  wire  aw_last = 8'h0 == len_1; // @[Fragmenter.scala 110:27]
  reg [8:0] w_counter; // @[Fragmenter.scala 164:30]
  wire  w_idle = w_counter == 9'h0; // @[Fragmenter.scala 165:30]
  reg  wbeats_latched; // @[Fragmenter.scala 150:35]
  wire  _in_aw_ready_T = w_idle | wbeats_latched; // @[Fragmenter.scala 158:52]
  wire  in_aw_ready = auto_out_aw_ready & (w_idle | wbeats_latched); // @[Fragmenter.scala 158:35]
  wire [11:0] _out_bits_addr_T_7 = ~addr_1; // @[Fragmenter.scala 122:28]
  wire [8:0] _out_bits_addr_T_9 = 9'h3 << irr_1_bits_size; // @[package.scala 234:77]
  wire [1:0] _out_bits_addr_T_11 = ~_out_bits_addr_T_9[1:0]; // @[package.scala 234:46]
  wire [11:0] _GEN_34 = {{10'd0}, _out_bits_addr_T_11}; // @[Fragmenter.scala 122:34]
  wire [11:0] _out_bits_addr_T_12 = _out_bits_addr_T_7 | _GEN_34; // @[Fragmenter.scala 122:34]
  wire  irr_1_valid = deq_1_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  wire  _T_5 = in_aw_ready & irr_1_valid; // @[Decoupled.scala 52:35]
  wire [8:0] _GEN_35 = {{1'd0}, len_1}; // @[Fragmenter.scala 127:25]
  wire [8:0] _r_len_T_3 = _GEN_35 - 9'h1; // @[Fragmenter.scala 127:25]
  wire [15:0] _GEN_8 = _T_5 ? mux_addr_1 : {{4'd0}, r_addr_1}; // @[Fragmenter.scala 124:27 126:18 61:25]
  wire [8:0] _GEN_9 = _T_5 ? _r_len_T_3 : {{1'd0}, r_len_1}; // @[Fragmenter.scala 124:27 127:18 62:25]
  wire  wbeats_valid = irr_1_valid & ~wbeats_latched; // @[Fragmenter.scala 159:35]
  wire  _GEN_10 = wbeats_valid & w_idle | wbeats_latched; // @[Fragmenter.scala 150:35 153:{43,60}]
  wire  bundleOut_0_aw_valid = irr_1_valid & _in_aw_ready_T; // @[Fragmenter.scala 157:35]
  wire  _T_7 = auto_out_aw_ready & bundleOut_0_aw_valid; // @[Decoupled.scala 52:35]
  wire [8:0] _w_todo_T = wbeats_valid ? 9'h1 : 9'h0; // @[Fragmenter.scala 166:35]
  wire [8:0] w_todo = w_idle ? _w_todo_T : w_counter; // @[Fragmenter.scala 166:23]
  wire  w_last = w_todo == 9'h1; // @[Fragmenter.scala 167:27]
  wire  in_w_valid = in_w_deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  wire  _bundleOut_0_w_valid_T_1 = ~w_idle | wbeats_valid; // @[Fragmenter.scala 173:51]
  wire  bundleOut_0_w_valid = in_w_valid & (~w_idle | wbeats_valid); // @[Fragmenter.scala 173:33]
  wire  _w_counter_T = auto_out_w_ready & bundleOut_0_w_valid; // @[Decoupled.scala 52:35]
  wire [8:0] _GEN_36 = {{8'd0}, _w_counter_T}; // @[Fragmenter.scala 168:27]
  wire [8:0] _w_counter_T_2 = w_todo - _GEN_36; // @[Fragmenter.scala 168:27]
  wire  _T_13 = ~reset; // @[Fragmenter.scala 169:14]
  wire  in_w_bits_last = in_w_deq_io_deq_bits_last; // @[Decoupled.scala 417:19 418:14]
  wire  bundleOut_0_b_ready = auto_in_b_ready | ~auto_out_b_bits_echo_real_last; // @[Fragmenter.scala 189:33]
  reg [1:0] error_0; // @[Fragmenter.scala 192:26]
  reg [1:0] error_1; // @[Fragmenter.scala 192:26]
  wire [1:0] _GEN_13 = auto_out_b_bits_id ? error_1 : error_0; // @[Fragmenter.scala 193:{41,41}]
  wire [1:0] _T_22 = 2'h1 << auto_out_b_bits_id; // @[OneHot.scala 64:12]
  wire  _T_26 = bundleOut_0_b_ready & auto_out_b_valid; // @[Decoupled.scala 52:35]
  wire [1:0] _error_0_T = error_0 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70]
  wire [1:0] _error_1_T = error_1 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70]
  Queue deq ( // @[Decoupled.scala 377:21]
    .clock(deq_clock),
    .reset(deq_reset),
    .io_enq_ready(deq_io_enq_ready),
    .io_enq_valid(deq_io_enq_valid),
    .io_enq_bits_id(deq_io_enq_bits_id),
    .io_enq_bits_addr(deq_io_enq_bits_addr),
    .io_enq_bits_len(deq_io_enq_bits_len),
    .io_enq_bits_size(deq_io_enq_bits_size),
    .io_enq_bits_burst(deq_io_enq_bits_burst),
    .io_enq_bits_echo_tl_state_size(deq_io_enq_bits_echo_tl_state_size),
    .io_enq_bits_echo_tl_state_source(deq_io_enq_bits_echo_tl_state_source),
    .io_deq_ready(deq_io_deq_ready),
    .io_deq_valid(deq_io_deq_valid),
    .io_deq_bits_id(deq_io_deq_bits_id),
    .io_deq_bits_addr(deq_io_deq_bits_addr),
    .io_deq_bits_len(deq_io_deq_bits_len),
    .io_deq_bits_size(deq_io_deq_bits_size),
    .io_deq_bits_burst(deq_io_deq_bits_burst),
    .io_deq_bits_echo_tl_state_size(deq_io_deq_bits_echo_tl_state_size),
    .io_deq_bits_echo_tl_state_source(deq_io_deq_bits_echo_tl_state_source)
  );
  Queue deq_1 ( // @[Decoupled.scala 377:21]
    .clock(deq_1_clock),
    .reset(deq_1_reset),
    .io_enq_ready(deq_1_io_enq_ready),
    .io_enq_valid(deq_1_io_enq_valid),
    .io_enq_bits_id(deq_1_io_enq_bits_id),
    .io_enq_bits_addr(deq_1_io_enq_bits_addr),
    .io_enq_bits_len(deq_1_io_enq_bits_len),
    .io_enq_bits_size(deq_1_io_enq_bits_size),
    .io_enq_bits_burst(deq_1_io_enq_bits_burst),
    .io_enq_bits_echo_tl_state_size(deq_1_io_enq_bits_echo_tl_state_size),
    .io_enq_bits_echo_tl_state_source(deq_1_io_enq_bits_echo_tl_state_source),
    .io_deq_ready(deq_1_io_deq_ready),
    .io_deq_valid(deq_1_io_deq_valid),
    .io_deq_bits_id(deq_1_io_deq_bits_id),
    .io_deq_bits_addr(deq_1_io_deq_bits_addr),
    .io_deq_bits_len(deq_1_io_deq_bits_len),
    .io_deq_bits_size(deq_1_io_deq_bits_size),
    .io_deq_bits_burst(deq_1_io_deq_bits_burst),
    .io_deq_bits_echo_tl_state_size(deq_1_io_deq_bits_echo_tl_state_size),
    .io_deq_bits_echo_tl_state_source(deq_1_io_deq_bits_echo_tl_state_source)
  );
  Queue_2 in_w_deq ( // @[Decoupled.scala 377:21]
    .clock(in_w_deq_clock),
    .reset(in_w_deq_reset),
    .io_enq_ready(in_w_deq_io_enq_ready),
    .io_enq_valid(in_w_deq_io_enq_valid),
    .io_enq_bits_data(in_w_deq_io_enq_bits_data),
    .io_enq_bits_strb(in_w_deq_io_enq_bits_strb),
    .io_enq_bits_last(in_w_deq_io_enq_bits_last),
    .io_deq_ready(in_w_deq_io_deq_ready),
    .io_deq_valid(in_w_deq_io_deq_valid),
    .io_deq_bits_data(in_w_deq_io_deq_bits_data),
    .io_deq_bits_strb(in_w_deq_io_deq_bits_strb),
    .io_deq_bits_last(in_w_deq_io_deq_bits_last)
  );
  assign auto_in_aw_ready = deq_1_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_w_ready = in_w_deq_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_b_valid = auto_out_b_valid & auto_out_b_bits_echo_real_last; // @[Fragmenter.scala 188:33]
  assign auto_in_b_bits_id = auto_out_b_bits_id; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_resp = auto_out_b_bits_resp | _GEN_13; // @[Fragmenter.scala 193:41]
  assign auto_in_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_ar_ready = deq_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_r_valid = auto_out_r_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_r_bits_id = auto_out_r_bits_id; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_r_bits_data = auto_out_r_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_r_bits_last = auto_out_r_bits_echo_real_last; // @[Fragmenter.scala 183:41]
  assign auto_out_aw_valid = irr_1_valid & _in_aw_ready_T; // @[Fragmenter.scala 157:35]
  assign auto_out_aw_bits_id = deq_1_io_deq_bits_id; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_addr = ~_out_bits_addr_T_12; // @[Fragmenter.scala 122:26]
  assign auto_out_aw_bits_echo_tl_state_size = deq_1_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_echo_tl_state_source = deq_1_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_echo_real_last = 8'h0 == len_1; // @[Fragmenter.scala 110:27]
  assign auto_out_w_valid = in_w_valid & (~w_idle | wbeats_valid); // @[Fragmenter.scala 173:33]
  assign auto_out_w_bits_data = in_w_deq_io_deq_bits_data; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_w_bits_strb = in_w_deq_io_deq_bits_strb; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_b_ready = auto_in_b_ready | ~auto_out_b_bits_echo_real_last; // @[Fragmenter.scala 189:33]
  assign auto_out_ar_valid = deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  assign auto_out_ar_bits_id = deq_io_deq_bits_id; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_addr = ~_out_bits_addr_T_5; // @[Fragmenter.scala 122:26]
  assign auto_out_ar_bits_echo_tl_state_size = deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_echo_tl_state_source = deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_echo_real_last = 8'h0 == len; // @[Fragmenter.scala 110:27]
  assign auto_out_r_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_clock = clock;
  assign deq_reset = reset;
  assign deq_io_enq_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_deq_ready = auto_out_ar_ready & ar_last; // @[Fragmenter.scala 111:30]
  assign deq_1_clock = clock;
  assign deq_1_reset = reset;
  assign deq_1_io_enq_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_1_io_enq_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_1_io_enq_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_1_io_enq_bits_len = auto_in_aw_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_1_io_enq_bits_size = auto_in_aw_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_1_io_enq_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_1_io_enq_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_1_io_enq_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_1_io_deq_ready = in_aw_ready & aw_last; // @[Fragmenter.scala 111:30]
  assign in_w_deq_clock = clock;
  assign in_w_deq_reset = reset;
  assign in_w_deq_io_enq_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign in_w_deq_io_enq_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign in_w_deq_io_enq_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign in_w_deq_io_enq_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign in_w_deq_io_deq_ready = auto_out_w_ready & _bundleOut_0_w_valid_T_1; // @[Fragmenter.scala 174:33]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 60:29]
      busy <= 1'h0; // @[Fragmenter.scala 60:29]
    end else if (_T_2) begin // @[Fragmenter.scala 124:27]
      busy <= ~ar_last; // @[Fragmenter.scala 125:16]
    end
    r_addr <= _GEN_3[11:0];
    r_len <= _GEN_4[7:0];
    if (reset) begin // @[Fragmenter.scala 60:29]
      busy_1 <= 1'h0; // @[Fragmenter.scala 60:29]
    end else if (_T_5) begin // @[Fragmenter.scala 124:27]
      busy_1 <= ~aw_last; // @[Fragmenter.scala 125:16]
    end
    r_addr_1 <= _GEN_8[11:0];
    r_len_1 <= _GEN_9[7:0];
    if (reset) begin // @[Fragmenter.scala 164:30]
      w_counter <= 9'h0; // @[Fragmenter.scala 164:30]
    end else begin
      w_counter <= _w_counter_T_2; // @[Fragmenter.scala 168:17]
    end
    if (reset) begin // @[Fragmenter.scala 150:35]
      wbeats_latched <= 1'h0; // @[Fragmenter.scala 150:35]
    end else if (_T_7) begin // @[Fragmenter.scala 154:28]
      wbeats_latched <= 1'h0; // @[Fragmenter.scala 154:45]
    end else begin
      wbeats_latched <= _GEN_10;
    end
    if (reset) begin // @[Fragmenter.scala 192:26]
      error_0 <= 2'h0; // @[Fragmenter.scala 192:26]
    end else if (_T_22[0] & _T_26) begin // @[Fragmenter.scala 195:36]
      if (auto_out_b_bits_echo_real_last) begin // @[Fragmenter.scala 195:48]
        error_0 <= 2'h0;
      end else begin
        error_0 <= _error_0_T;
      end
    end
    if (reset) begin // @[Fragmenter.scala 192:26]
      error_1 <= 2'h0; // @[Fragmenter.scala 192:26]
    end else if (_T_22[1] & _T_26) begin // @[Fragmenter.scala 195:36]
      if (auto_out_b_bits_echo_real_last) begin // @[Fragmenter.scala 195:48]
        error_1 <= 2'h0;
      end else begin
        error_1 <= _error_1_T;
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~_w_counter_T | w_todo != 9'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:169 assert (!out.w.fire() || w_todo =/= UInt(0)) // underflow impossible\n"
            ); // @[Fragmenter.scala 169:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_w_counter_T | w_todo != 9'h0) & ~reset) begin
          $fatal; // @[Fragmenter.scala 169:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_13 & ~(~bundleOut_0_w_valid | ~in_w_bits_last | w_last)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:178 assert (!out.w.valid || !in_w.bits.last || w_last)\n"); // @[Fragmenter.scala 178:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~bundleOut_0_w_valid | ~in_w_bits_last | w_last) & _T_13) begin
          $fatal; // @[Fragmenter.scala 178:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  busy = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  r_addr = _RAND_1[11:0];
  _RAND_2 = {1{`RANDOM}};
  r_len = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  busy_1 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  r_addr_1 = _RAND_4[11:0];
  _RAND_5 = {1{`RANDOM}};
  r_len_1 = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  w_counter = _RAND_6[8:0];
  _RAND_7 = {1{`RANDOM}};
  wbeats_latched = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  error_0 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  error_1 = _RAND_9[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_5(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input        io_enq_bits_id,
  input  [1:0] io_enq_bits_resp,
  input  [3:0] io_enq_bits_echo_tl_state_size,
  input  [1:0] io_enq_bits_echo_tl_state_source,
  input        io_deq_ready,
  output       io_deq_valid,
  output       io_deq_bits_id,
  output [1:0] io_deq_bits_resp,
  output [3:0] io_deq_bits_echo_tl_state_size,
  output [1:0] io_deq_bits_echo_tl_state_source
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  reg  ram_id [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_resp [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_resp_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_resp_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_resp_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_resp_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_resp_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_resp_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_resp_MPORT_en; // @[Decoupled.scala 275:95]
  reg [3:0] ram_echo_tl_state_size [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_echo_tl_state_source [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_12 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_12 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_id_io_deq_bits_MPORT_en = 1'h1;
  assign ram_id_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_id_io_deq_bits_MPORT_data = ram_id[ram_id_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_id_MPORT_data = io_enq_bits_id;
  assign ram_id_MPORT_addr = 1'h0;
  assign ram_id_MPORT_mask = 1'h1;
  assign ram_id_MPORT_en = empty ? _GEN_12 : _do_enq_T;
  assign ram_resp_io_deq_bits_MPORT_en = 1'h1;
  assign ram_resp_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_resp_io_deq_bits_MPORT_data = ram_resp[ram_resp_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_resp_MPORT_data = io_enq_bits_resp;
  assign ram_resp_MPORT_addr = 1'h0;
  assign ram_resp_MPORT_mask = 1'h1;
  assign ram_resp_MPORT_en = empty ? _GEN_12 : _do_enq_T;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_data =
    ram_echo_tl_state_size[ram_echo_tl_state_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_size_MPORT_data = io_enq_bits_echo_tl_state_size;
  assign ram_echo_tl_state_size_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_size_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_size_MPORT_en = empty ? _GEN_12 : _do_enq_T;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_data =
    ram_echo_tl_state_source[ram_echo_tl_state_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_source_MPORT_data = io_enq_bits_echo_tl_state_source;
  assign ram_echo_tl_state_source_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_source_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_source_MPORT_en = empty ? _GEN_12 : _do_enq_T;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_id = empty ? io_enq_bits_id : ram_id_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_resp = empty ? io_enq_bits_resp : ram_resp_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_echo_tl_state_size = empty ? io_enq_bits_echo_tl_state_size :
    ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_echo_tl_state_source = empty ? io_enq_bits_echo_tl_state_source :
    ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_id_MPORT_en & ram_id_MPORT_mask) begin
      ram_id[ram_id_MPORT_addr] <= ram_id_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_resp_MPORT_en & ram_resp_MPORT_mask) begin
      ram_resp[ram_resp_MPORT_addr] <= ram_resp_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_size_MPORT_en & ram_echo_tl_state_size_MPORT_mask) begin
      ram_echo_tl_state_size[ram_echo_tl_state_size_MPORT_addr] <= ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_source_MPORT_en & ram_echo_tl_state_source_MPORT_mask) begin
      ram_echo_tl_state_source[ram_echo_tl_state_source_MPORT_addr] <= ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_id[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_resp[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_echo_tl_state_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_echo_tl_state_source[initvar] = _RAND_3[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_4 = {1{`RANDOM}};
  maybe_full = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_7(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_id,
  input  [31:0] io_enq_bits_data,
  input  [1:0]  io_enq_bits_resp,
  input  [3:0]  io_enq_bits_echo_tl_state_size,
  input  [1:0]  io_enq_bits_echo_tl_state_source,
  input         io_enq_bits_last,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_id,
  output [31:0] io_deq_bits_data,
  output [1:0]  io_deq_bits_resp,
  output [3:0]  io_deq_bits_echo_tl_state_size,
  output [1:0]  io_deq_bits_echo_tl_state_source,
  output        io_deq_bits_last
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  reg  ram_id [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_en; // @[Decoupled.scala 275:95]
  reg [31:0] ram_data [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_resp [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_resp_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_resp_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_resp_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_resp_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_resp_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_resp_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_resp_MPORT_en; // @[Decoupled.scala 275:95]
  reg [3:0] ram_echo_tl_state_size [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_echo_tl_state_source [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_last [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_last_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_last_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_last_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_14 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_14 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_id_io_deq_bits_MPORT_en = 1'h1;
  assign ram_id_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_id_io_deq_bits_MPORT_data = ram_id[ram_id_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_id_MPORT_data = io_enq_bits_id;
  assign ram_id_MPORT_addr = 1'h0;
  assign ram_id_MPORT_mask = 1'h1;
  assign ram_id_MPORT_en = empty ? _GEN_14 : _do_enq_T;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = 1'h0;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = empty ? _GEN_14 : _do_enq_T;
  assign ram_resp_io_deq_bits_MPORT_en = 1'h1;
  assign ram_resp_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_resp_io_deq_bits_MPORT_data = ram_resp[ram_resp_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_resp_MPORT_data = io_enq_bits_resp;
  assign ram_resp_MPORT_addr = 1'h0;
  assign ram_resp_MPORT_mask = 1'h1;
  assign ram_resp_MPORT_en = empty ? _GEN_14 : _do_enq_T;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_data =
    ram_echo_tl_state_size[ram_echo_tl_state_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_size_MPORT_data = io_enq_bits_echo_tl_state_size;
  assign ram_echo_tl_state_size_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_size_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_size_MPORT_en = empty ? _GEN_14 : _do_enq_T;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_data =
    ram_echo_tl_state_source[ram_echo_tl_state_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_source_MPORT_data = io_enq_bits_echo_tl_state_source;
  assign ram_echo_tl_state_source_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_source_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_source_MPORT_en = empty ? _GEN_14 : _do_enq_T;
  assign ram_last_io_deq_bits_MPORT_en = 1'h1;
  assign ram_last_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_last_io_deq_bits_MPORT_data = ram_last[ram_last_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_last_MPORT_data = io_enq_bits_last;
  assign ram_last_MPORT_addr = 1'h0;
  assign ram_last_MPORT_mask = 1'h1;
  assign ram_last_MPORT_en = empty ? _GEN_14 : _do_enq_T;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_id = empty ? io_enq_bits_id : ram_id_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_data = empty ? io_enq_bits_data : ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_resp = empty ? io_enq_bits_resp : ram_resp_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_echo_tl_state_size = empty ? io_enq_bits_echo_tl_state_size :
    ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_echo_tl_state_source = empty ? io_enq_bits_echo_tl_state_source :
    ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_last = empty ? io_enq_bits_last : ram_last_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_id_MPORT_en & ram_id_MPORT_mask) begin
      ram_id[ram_id_MPORT_addr] <= ram_id_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_resp_MPORT_en & ram_resp_MPORT_mask) begin
      ram_resp[ram_resp_MPORT_addr] <= ram_resp_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_size_MPORT_en & ram_echo_tl_state_size_MPORT_mask) begin
      ram_echo_tl_state_size[ram_echo_tl_state_size_MPORT_addr] <= ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_source_MPORT_en & ram_echo_tl_state_source_MPORT_mask) begin
      ram_echo_tl_state_source[ram_echo_tl_state_source_MPORT_addr] <= ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_last_MPORT_en & ram_last_MPORT_mask) begin
      ram_last[ram_last_MPORT_addr] <= ram_last_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_id[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_data[initvar] = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_resp[initvar] = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_echo_tl_state_size[initvar] = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_echo_tl_state_source[initvar] = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_last[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_6 = {1{`RANDOM}};
  maybe_full = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AXI4Buffer(
  input         clock,
  input         reset,
  output        auto_in_aw_ready,
  input         auto_in_aw_valid,
  input         auto_in_aw_bits_id,
  input  [11:0] auto_in_aw_bits_addr,
  input  [7:0]  auto_in_aw_bits_len,
  input  [2:0]  auto_in_aw_bits_size,
  input  [1:0]  auto_in_aw_bits_burst,
  input  [3:0]  auto_in_aw_bits_echo_tl_state_size,
  input  [1:0]  auto_in_aw_bits_echo_tl_state_source,
  output        auto_in_w_ready,
  input         auto_in_w_valid,
  input  [31:0] auto_in_w_bits_data,
  input  [3:0]  auto_in_w_bits_strb,
  input         auto_in_w_bits_last,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output        auto_in_b_bits_id,
  output [1:0]  auto_in_b_bits_resp,
  output [3:0]  auto_in_b_bits_echo_tl_state_size,
  output [1:0]  auto_in_b_bits_echo_tl_state_source,
  output        auto_in_ar_ready,
  input         auto_in_ar_valid,
  input         auto_in_ar_bits_id,
  input  [11:0] auto_in_ar_bits_addr,
  input  [7:0]  auto_in_ar_bits_len,
  input  [2:0]  auto_in_ar_bits_size,
  input  [1:0]  auto_in_ar_bits_burst,
  input  [3:0]  auto_in_ar_bits_echo_tl_state_size,
  input  [1:0]  auto_in_ar_bits_echo_tl_state_source,
  input         auto_in_r_ready,
  output        auto_in_r_valid,
  output        auto_in_r_bits_id,
  output [31:0] auto_in_r_bits_data,
  output [1:0]  auto_in_r_bits_resp,
  output [3:0]  auto_in_r_bits_echo_tl_state_size,
  output [1:0]  auto_in_r_bits_echo_tl_state_source,
  output        auto_in_r_bits_last,
  input         auto_out_aw_ready,
  output        auto_out_aw_valid,
  output        auto_out_aw_bits_id,
  output [11:0] auto_out_aw_bits_addr,
  output [7:0]  auto_out_aw_bits_len,
  output [2:0]  auto_out_aw_bits_size,
  output [1:0]  auto_out_aw_bits_burst,
  output [3:0]  auto_out_aw_bits_echo_tl_state_size,
  output [1:0]  auto_out_aw_bits_echo_tl_state_source,
  input         auto_out_w_ready,
  output        auto_out_w_valid,
  output [31:0] auto_out_w_bits_data,
  output [3:0]  auto_out_w_bits_strb,
  output        auto_out_w_bits_last,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input         auto_out_b_bits_id,
  input  [1:0]  auto_out_b_bits_resp,
  input  [3:0]  auto_out_b_bits_echo_tl_state_size,
  input  [1:0]  auto_out_b_bits_echo_tl_state_source,
  input         auto_out_ar_ready,
  output        auto_out_ar_valid,
  output        auto_out_ar_bits_id,
  output [11:0] auto_out_ar_bits_addr,
  output [7:0]  auto_out_ar_bits_len,
  output [2:0]  auto_out_ar_bits_size,
  output [1:0]  auto_out_ar_bits_burst,
  output [3:0]  auto_out_ar_bits_echo_tl_state_size,
  output [1:0]  auto_out_ar_bits_echo_tl_state_source,
  output        auto_out_r_ready,
  input         auto_out_r_valid,
  input         auto_out_r_bits_id,
  input  [31:0] auto_out_r_bits_data,
  input  [1:0]  auto_out_r_bits_resp,
  input  [3:0]  auto_out_r_bits_echo_tl_state_size,
  input  [1:0]  auto_out_r_bits_echo_tl_state_source,
  input         auto_out_r_bits_last
);
  wire  bundleOut_0_aw_deq_clock; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_aw_deq_reset; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_aw_deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_aw_deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_aw_deq_io_enq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] bundleOut_0_aw_deq_io_enq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_aw_deq_io_enq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_aw_deq_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleOut_0_aw_deq_io_enq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] bundleOut_0_aw_deq_io_enq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleOut_0_aw_deq_io_enq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_aw_deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_aw_deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_aw_deq_io_deq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] bundleOut_0_aw_deq_io_deq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_aw_deq_io_deq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_aw_deq_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleOut_0_aw_deq_io_deq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] bundleOut_0_aw_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleOut_0_aw_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_w_deq_clock; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_w_deq_reset; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_w_deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_w_deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_w_deq_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire [3:0] bundleOut_0_w_deq_io_enq_bits_strb; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_w_deq_io_enq_bits_last; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_w_deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_w_deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [31:0] bundleOut_0_w_deq_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire [3:0] bundleOut_0_w_deq_io_deq_bits_strb; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_w_deq_io_deq_bits_last; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_deq_clock; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_deq_reset; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_deq_io_enq_bits_id; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_b_deq_io_enq_bits_resp; // @[Decoupled.scala 377:21]
  wire [3:0] bundleIn_0_b_deq_io_enq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_b_deq_io_enq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_b_deq_io_deq_bits_id; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_b_deq_io_deq_bits_resp; // @[Decoupled.scala 377:21]
  wire [3:0] bundleIn_0_b_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_b_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_ar_deq_clock; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_ar_deq_reset; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_ar_deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_ar_deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_ar_deq_io_enq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] bundleOut_0_ar_deq_io_enq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_ar_deq_io_enq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_ar_deq_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleOut_0_ar_deq_io_enq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] bundleOut_0_ar_deq_io_enq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleOut_0_ar_deq_io_enq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_ar_deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_ar_deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire  bundleOut_0_ar_deq_io_deq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] bundleOut_0_ar_deq_io_deq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] bundleOut_0_ar_deq_io_deq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] bundleOut_0_ar_deq_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleOut_0_ar_deq_io_deq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] bundleOut_0_ar_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleOut_0_ar_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_clock; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_reset; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_io_enq_bits_id; // @[Decoupled.scala 377:21]
  wire [31:0] bundleIn_0_r_deq_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_r_deq_io_enq_bits_resp; // @[Decoupled.scala 377:21]
  wire [3:0] bundleIn_0_r_deq_io_enq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_r_deq_io_enq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_io_enq_bits_last; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_io_deq_bits_id; // @[Decoupled.scala 377:21]
  wire [31:0] bundleIn_0_r_deq_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_r_deq_io_deq_bits_resp; // @[Decoupled.scala 377:21]
  wire [3:0] bundleIn_0_r_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] bundleIn_0_r_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  bundleIn_0_r_deq_io_deq_bits_last; // @[Decoupled.scala 377:21]
  Queue bundleOut_0_aw_deq ( // @[Decoupled.scala 377:21]
    .clock(bundleOut_0_aw_deq_clock),
    .reset(bundleOut_0_aw_deq_reset),
    .io_enq_ready(bundleOut_0_aw_deq_io_enq_ready),
    .io_enq_valid(bundleOut_0_aw_deq_io_enq_valid),
    .io_enq_bits_id(bundleOut_0_aw_deq_io_enq_bits_id),
    .io_enq_bits_addr(bundleOut_0_aw_deq_io_enq_bits_addr),
    .io_enq_bits_len(bundleOut_0_aw_deq_io_enq_bits_len),
    .io_enq_bits_size(bundleOut_0_aw_deq_io_enq_bits_size),
    .io_enq_bits_burst(bundleOut_0_aw_deq_io_enq_bits_burst),
    .io_enq_bits_echo_tl_state_size(bundleOut_0_aw_deq_io_enq_bits_echo_tl_state_size),
    .io_enq_bits_echo_tl_state_source(bundleOut_0_aw_deq_io_enq_bits_echo_tl_state_source),
    .io_deq_ready(bundleOut_0_aw_deq_io_deq_ready),
    .io_deq_valid(bundleOut_0_aw_deq_io_deq_valid),
    .io_deq_bits_id(bundleOut_0_aw_deq_io_deq_bits_id),
    .io_deq_bits_addr(bundleOut_0_aw_deq_io_deq_bits_addr),
    .io_deq_bits_len(bundleOut_0_aw_deq_io_deq_bits_len),
    .io_deq_bits_size(bundleOut_0_aw_deq_io_deq_bits_size),
    .io_deq_bits_burst(bundleOut_0_aw_deq_io_deq_bits_burst),
    .io_deq_bits_echo_tl_state_size(bundleOut_0_aw_deq_io_deq_bits_echo_tl_state_size),
    .io_deq_bits_echo_tl_state_source(bundleOut_0_aw_deq_io_deq_bits_echo_tl_state_source)
  );
  Queue_2 bundleOut_0_w_deq ( // @[Decoupled.scala 377:21]
    .clock(bundleOut_0_w_deq_clock),
    .reset(bundleOut_0_w_deq_reset),
    .io_enq_ready(bundleOut_0_w_deq_io_enq_ready),
    .io_enq_valid(bundleOut_0_w_deq_io_enq_valid),
    .io_enq_bits_data(bundleOut_0_w_deq_io_enq_bits_data),
    .io_enq_bits_strb(bundleOut_0_w_deq_io_enq_bits_strb),
    .io_enq_bits_last(bundleOut_0_w_deq_io_enq_bits_last),
    .io_deq_ready(bundleOut_0_w_deq_io_deq_ready),
    .io_deq_valid(bundleOut_0_w_deq_io_deq_valid),
    .io_deq_bits_data(bundleOut_0_w_deq_io_deq_bits_data),
    .io_deq_bits_strb(bundleOut_0_w_deq_io_deq_bits_strb),
    .io_deq_bits_last(bundleOut_0_w_deq_io_deq_bits_last)
  );
  Queue_5 bundleIn_0_b_deq ( // @[Decoupled.scala 377:21]
    .clock(bundleIn_0_b_deq_clock),
    .reset(bundleIn_0_b_deq_reset),
    .io_enq_ready(bundleIn_0_b_deq_io_enq_ready),
    .io_enq_valid(bundleIn_0_b_deq_io_enq_valid),
    .io_enq_bits_id(bundleIn_0_b_deq_io_enq_bits_id),
    .io_enq_bits_resp(bundleIn_0_b_deq_io_enq_bits_resp),
    .io_enq_bits_echo_tl_state_size(bundleIn_0_b_deq_io_enq_bits_echo_tl_state_size),
    .io_enq_bits_echo_tl_state_source(bundleIn_0_b_deq_io_enq_bits_echo_tl_state_source),
    .io_deq_ready(bundleIn_0_b_deq_io_deq_ready),
    .io_deq_valid(bundleIn_0_b_deq_io_deq_valid),
    .io_deq_bits_id(bundleIn_0_b_deq_io_deq_bits_id),
    .io_deq_bits_resp(bundleIn_0_b_deq_io_deq_bits_resp),
    .io_deq_bits_echo_tl_state_size(bundleIn_0_b_deq_io_deq_bits_echo_tl_state_size),
    .io_deq_bits_echo_tl_state_source(bundleIn_0_b_deq_io_deq_bits_echo_tl_state_source)
  );
  Queue bundleOut_0_ar_deq ( // @[Decoupled.scala 377:21]
    .clock(bundleOut_0_ar_deq_clock),
    .reset(bundleOut_0_ar_deq_reset),
    .io_enq_ready(bundleOut_0_ar_deq_io_enq_ready),
    .io_enq_valid(bundleOut_0_ar_deq_io_enq_valid),
    .io_enq_bits_id(bundleOut_0_ar_deq_io_enq_bits_id),
    .io_enq_bits_addr(bundleOut_0_ar_deq_io_enq_bits_addr),
    .io_enq_bits_len(bundleOut_0_ar_deq_io_enq_bits_len),
    .io_enq_bits_size(bundleOut_0_ar_deq_io_enq_bits_size),
    .io_enq_bits_burst(bundleOut_0_ar_deq_io_enq_bits_burst),
    .io_enq_bits_echo_tl_state_size(bundleOut_0_ar_deq_io_enq_bits_echo_tl_state_size),
    .io_enq_bits_echo_tl_state_source(bundleOut_0_ar_deq_io_enq_bits_echo_tl_state_source),
    .io_deq_ready(bundleOut_0_ar_deq_io_deq_ready),
    .io_deq_valid(bundleOut_0_ar_deq_io_deq_valid),
    .io_deq_bits_id(bundleOut_0_ar_deq_io_deq_bits_id),
    .io_deq_bits_addr(bundleOut_0_ar_deq_io_deq_bits_addr),
    .io_deq_bits_len(bundleOut_0_ar_deq_io_deq_bits_len),
    .io_deq_bits_size(bundleOut_0_ar_deq_io_deq_bits_size),
    .io_deq_bits_burst(bundleOut_0_ar_deq_io_deq_bits_burst),
    .io_deq_bits_echo_tl_state_size(bundleOut_0_ar_deq_io_deq_bits_echo_tl_state_size),
    .io_deq_bits_echo_tl_state_source(bundleOut_0_ar_deq_io_deq_bits_echo_tl_state_source)
  );
  Queue_7 bundleIn_0_r_deq ( // @[Decoupled.scala 377:21]
    .clock(bundleIn_0_r_deq_clock),
    .reset(bundleIn_0_r_deq_reset),
    .io_enq_ready(bundleIn_0_r_deq_io_enq_ready),
    .io_enq_valid(bundleIn_0_r_deq_io_enq_valid),
    .io_enq_bits_id(bundleIn_0_r_deq_io_enq_bits_id),
    .io_enq_bits_data(bundleIn_0_r_deq_io_enq_bits_data),
    .io_enq_bits_resp(bundleIn_0_r_deq_io_enq_bits_resp),
    .io_enq_bits_echo_tl_state_size(bundleIn_0_r_deq_io_enq_bits_echo_tl_state_size),
    .io_enq_bits_echo_tl_state_source(bundleIn_0_r_deq_io_enq_bits_echo_tl_state_source),
    .io_enq_bits_last(bundleIn_0_r_deq_io_enq_bits_last),
    .io_deq_ready(bundleIn_0_r_deq_io_deq_ready),
    .io_deq_valid(bundleIn_0_r_deq_io_deq_valid),
    .io_deq_bits_id(bundleIn_0_r_deq_io_deq_bits_id),
    .io_deq_bits_data(bundleIn_0_r_deq_io_deq_bits_data),
    .io_deq_bits_resp(bundleIn_0_r_deq_io_deq_bits_resp),
    .io_deq_bits_echo_tl_state_size(bundleIn_0_r_deq_io_deq_bits_echo_tl_state_size),
    .io_deq_bits_echo_tl_state_source(bundleIn_0_r_deq_io_deq_bits_echo_tl_state_source),
    .io_deq_bits_last(bundleIn_0_r_deq_io_deq_bits_last)
  );
  assign auto_in_aw_ready = bundleOut_0_aw_deq_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_w_ready = bundleOut_0_w_deq_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_b_valid = bundleIn_0_b_deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  assign auto_in_b_bits_id = bundleIn_0_b_deq_io_deq_bits_id; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_b_bits_resp = bundleIn_0_b_deq_io_deq_bits_resp; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_b_bits_echo_tl_state_size = bundleIn_0_b_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_b_bits_echo_tl_state_source = bundleIn_0_b_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_ar_ready = bundleOut_0_ar_deq_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 381:17]
  assign auto_in_r_valid = bundleIn_0_r_deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  assign auto_in_r_bits_id = bundleIn_0_r_deq_io_deq_bits_id; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_r_bits_data = bundleIn_0_r_deq_io_deq_bits_data; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_r_bits_resp = bundleIn_0_r_deq_io_deq_bits_resp; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_r_bits_echo_tl_state_size = bundleIn_0_r_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_r_bits_echo_tl_state_source = bundleIn_0_r_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 417:19 418:14]
  assign auto_in_r_bits_last = bundleIn_0_r_deq_io_deq_bits_last; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_valid = bundleOut_0_aw_deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  assign auto_out_aw_bits_id = bundleOut_0_aw_deq_io_deq_bits_id; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_addr = bundleOut_0_aw_deq_io_deq_bits_addr; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_len = bundleOut_0_aw_deq_io_deq_bits_len; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_size = bundleOut_0_aw_deq_io_deq_bits_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_burst = bundleOut_0_aw_deq_io_deq_bits_burst; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_echo_tl_state_size = bundleOut_0_aw_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_echo_tl_state_source = bundleOut_0_aw_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_w_valid = bundleOut_0_w_deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  assign auto_out_w_bits_data = bundleOut_0_w_deq_io_deq_bits_data; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_w_bits_strb = bundleOut_0_w_deq_io_deq_bits_strb; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_w_bits_last = bundleOut_0_w_deq_io_deq_bits_last; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_b_ready = bundleIn_0_b_deq_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 381:17]
  assign auto_out_ar_valid = bundleOut_0_ar_deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  assign auto_out_ar_bits_id = bundleOut_0_ar_deq_io_deq_bits_id; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_addr = bundleOut_0_ar_deq_io_deq_bits_addr; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_len = bundleOut_0_ar_deq_io_deq_bits_len; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_size = bundleOut_0_ar_deq_io_deq_bits_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_burst = bundleOut_0_ar_deq_io_deq_bits_burst; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_echo_tl_state_size = bundleOut_0_ar_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_echo_tl_state_source = bundleOut_0_ar_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_r_ready = bundleIn_0_r_deq_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 381:17]
  assign bundleOut_0_aw_deq_clock = clock;
  assign bundleOut_0_aw_deq_reset = reset;
  assign bundleOut_0_aw_deq_io_enq_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_aw_deq_io_enq_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_aw_deq_io_enq_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_aw_deq_io_enq_bits_len = auto_in_aw_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_aw_deq_io_enq_bits_size = auto_in_aw_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_aw_deq_io_enq_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_aw_deq_io_enq_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_aw_deq_io_enq_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_aw_deq_io_deq_ready = auto_out_aw_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_w_deq_clock = clock;
  assign bundleOut_0_w_deq_reset = reset;
  assign bundleOut_0_w_deq_io_enq_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_w_deq_io_enq_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_w_deq_io_enq_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_w_deq_io_enq_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_w_deq_io_deq_ready = auto_out_w_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_deq_clock = clock;
  assign bundleIn_0_b_deq_reset = reset;
  assign bundleIn_0_b_deq_io_enq_valid = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_deq_io_enq_bits_id = auto_out_b_bits_id; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_deq_io_enq_bits_resp = auto_out_b_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_deq_io_enq_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_deq_io_enq_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_deq_io_deq_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_clock = clock;
  assign bundleOut_0_ar_deq_reset = reset;
  assign bundleOut_0_ar_deq_io_enq_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_io_enq_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_io_enq_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_io_enq_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_io_enq_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_io_enq_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_io_enq_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_io_enq_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_ar_deq_io_deq_ready = auto_out_ar_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_r_deq_clock = clock;
  assign bundleIn_0_r_deq_reset = reset;
  assign bundleIn_0_r_deq_io_enq_valid = auto_out_r_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_r_deq_io_enq_bits_id = auto_out_r_bits_id; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_r_deq_io_enq_bits_data = auto_out_r_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_r_deq_io_enq_bits_resp = auto_out_r_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_r_deq_io_enq_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_r_deq_io_enq_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_r_deq_io_enq_bits_last = auto_out_r_bits_last; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_r_deq_io_deq_ready = auto_in_r_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module LFSRNoiseMaker(
  input   clock,
  input   io_inc,
  output  io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (io_inc) begin // @[Fuzzer.scala 45:22]
      if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
        lfsrs_0 <= 64'h1;
      end else begin
        lfsrs_0 <= _lfsrs_lfsr_T_2;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LFSRNoiseMaker_1(
  input         clock,
  input         io_inc,
  output [11:0] io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[11:0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (io_inc) begin // @[Fuzzer.scala 45:22]
      if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
        lfsrs_0 <= 64'h1;
      end else begin
        lfsrs_0 <= _lfsrs_lfsr_T_2;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LFSRNoiseMaker_2(
  input        clock,
  output [7:0] io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[7:0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
      lfsrs_0 <= 64'h1;
    end else begin
      lfsrs_0 <= _lfsrs_lfsr_T_2;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LFSRNoiseMaker_3(
  input        clock,
  input        io_inc,
  output [2:0] io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[2:0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (io_inc) begin // @[Fuzzer.scala 45:22]
      if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
        lfsrs_0 <= 64'h1;
      end else begin
        lfsrs_0 <= _lfsrs_lfsr_T_2;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LFSRNoiseMaker_4(
  input        clock,
  input        io_inc,
  output [1:0] io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[1:0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (io_inc) begin // @[Fuzzer.scala 45:22]
      if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
        lfsrs_0 <= 64'h1;
      end else begin
        lfsrs_0 <= _lfsrs_lfsr_T_2;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LFSRNoiseMaker_6(
  input        clock,
  input        io_inc,
  output [3:0] io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[3:0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (io_inc) begin // @[Fuzzer.scala 45:22]
      if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
        lfsrs_0 <= 64'h1;
      end else begin
        lfsrs_0 <= _lfsrs_lfsr_T_2;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LFSRNoiseMaker_18(
  input         clock,
  input         io_inc,
  output [31:0] io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[31:0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (io_inc) begin // @[Fuzzer.scala 45:22]
      if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
        lfsrs_0 <= 64'h1;
      end else begin
        lfsrs_0 <= _lfsrs_lfsr_T_2;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LFSRNoiseMaker_27(
  input         clock,
  input         io_inc,
  output [15:0] io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[15:0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (io_inc) begin // @[Fuzzer.scala 45:22]
      if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
        lfsrs_0 <= 64'h1;
      end else begin
        lfsrs_0 <= _lfsrs_lfsr_T_2;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AXI4Delayer(
  input         clock,
  input         reset,
  output        auto_in_aw_ready,
  input         auto_in_aw_valid,
  input         auto_in_aw_bits_id,
  input  [11:0] auto_in_aw_bits_addr,
  input  [7:0]  auto_in_aw_bits_len,
  input  [2:0]  auto_in_aw_bits_size,
  input  [1:0]  auto_in_aw_bits_burst,
  input  [3:0]  auto_in_aw_bits_echo_tl_state_size,
  input  [1:0]  auto_in_aw_bits_echo_tl_state_source,
  output        auto_in_w_ready,
  input         auto_in_w_valid,
  input  [31:0] auto_in_w_bits_data,
  input  [3:0]  auto_in_w_bits_strb,
  input         auto_in_w_bits_last,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output        auto_in_b_bits_id,
  output [1:0]  auto_in_b_bits_resp,
  output [3:0]  auto_in_b_bits_echo_tl_state_size,
  output [1:0]  auto_in_b_bits_echo_tl_state_source,
  output        auto_in_ar_ready,
  input         auto_in_ar_valid,
  input         auto_in_ar_bits_id,
  input  [11:0] auto_in_ar_bits_addr,
  input  [7:0]  auto_in_ar_bits_len,
  input  [2:0]  auto_in_ar_bits_size,
  input  [1:0]  auto_in_ar_bits_burst,
  input  [3:0]  auto_in_ar_bits_echo_tl_state_size,
  input  [1:0]  auto_in_ar_bits_echo_tl_state_source,
  input         auto_in_r_ready,
  output        auto_in_r_valid,
  output        auto_in_r_bits_id,
  output [31:0] auto_in_r_bits_data,
  output [1:0]  auto_in_r_bits_resp,
  output [3:0]  auto_in_r_bits_echo_tl_state_size,
  output [1:0]  auto_in_r_bits_echo_tl_state_source,
  output        auto_in_r_bits_last,
  input         auto_out_aw_ready,
  output        auto_out_aw_valid,
  output        auto_out_aw_bits_id,
  output [11:0] auto_out_aw_bits_addr,
  output [7:0]  auto_out_aw_bits_len,
  output [2:0]  auto_out_aw_bits_size,
  output [1:0]  auto_out_aw_bits_burst,
  output [3:0]  auto_out_aw_bits_echo_tl_state_size,
  output [1:0]  auto_out_aw_bits_echo_tl_state_source,
  input         auto_out_w_ready,
  output        auto_out_w_valid,
  output [31:0] auto_out_w_bits_data,
  output [3:0]  auto_out_w_bits_strb,
  output        auto_out_w_bits_last,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input         auto_out_b_bits_id,
  input  [1:0]  auto_out_b_bits_resp,
  input  [3:0]  auto_out_b_bits_echo_tl_state_size,
  input  [1:0]  auto_out_b_bits_echo_tl_state_source,
  input         auto_out_ar_ready,
  output        auto_out_ar_valid,
  output        auto_out_ar_bits_id,
  output [11:0] auto_out_ar_bits_addr,
  output [7:0]  auto_out_ar_bits_len,
  output [2:0]  auto_out_ar_bits_size,
  output [1:0]  auto_out_ar_bits_burst,
  output [3:0]  auto_out_ar_bits_echo_tl_state_size,
  output [1:0]  auto_out_ar_bits_echo_tl_state_source,
  output        auto_out_r_ready,
  input         auto_out_r_valid,
  input         auto_out_r_bits_id,
  input  [31:0] auto_out_r_bits_data,
  input  [1:0]  auto_out_r_bits_resp,
  input  [3:0]  auto_out_r_bits_echo_tl_state_size,
  input  [1:0]  auto_out_r_bits_echo_tl_state_source,
  input         auto_out_r_bits_last
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  arnoise_id_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arnoise_id_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  arnoise_id_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  arnoise_addr_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arnoise_addr_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [11:0] arnoise_addr_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  arnoise_len_nm_clock; // @[Fuzzer.scala 68:20]
  wire [7:0] arnoise_len_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  arnoise_size_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arnoise_size_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [2:0] arnoise_size_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  arnoise_burst_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arnoise_burst_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [1:0] arnoise_burst_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  arnoise_lock_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arnoise_lock_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  arnoise_lock_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  arnoise_cache_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arnoise_cache_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] arnoise_cache_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  arnoise_prot_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arnoise_prot_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [2:0] arnoise_prot_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  arnoise_qos_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arnoise_qos_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] arnoise_qos_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_id_nm_clock; // @[Fuzzer.scala 68:20]
  wire  awnoise_id_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  awnoise_id_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_addr_nm_clock; // @[Fuzzer.scala 68:20]
  wire  awnoise_addr_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [11:0] awnoise_addr_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_len_nm_clock; // @[Fuzzer.scala 68:20]
  wire [7:0] awnoise_len_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_size_nm_clock; // @[Fuzzer.scala 68:20]
  wire  awnoise_size_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [2:0] awnoise_size_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_burst_nm_clock; // @[Fuzzer.scala 68:20]
  wire  awnoise_burst_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [1:0] awnoise_burst_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_lock_nm_clock; // @[Fuzzer.scala 68:20]
  wire  awnoise_lock_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  awnoise_lock_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_cache_nm_clock; // @[Fuzzer.scala 68:20]
  wire  awnoise_cache_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] awnoise_cache_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_prot_nm_clock; // @[Fuzzer.scala 68:20]
  wire  awnoise_prot_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [2:0] awnoise_prot_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  awnoise_qos_nm_clock; // @[Fuzzer.scala 68:20]
  wire  awnoise_qos_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] awnoise_qos_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  wnoise_data_nm_clock; // @[Fuzzer.scala 68:20]
  wire  wnoise_data_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [31:0] wnoise_data_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  wnoise_strb_nm_clock; // @[Fuzzer.scala 68:20]
  wire  wnoise_strb_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] wnoise_strb_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  wnoise_last_nm_clock; // @[Fuzzer.scala 68:20]
  wire  wnoise_last_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  wnoise_last_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  rnoise_id_nm_clock; // @[Fuzzer.scala 68:20]
  wire  rnoise_id_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  rnoise_id_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  rnoise_data_nm_clock; // @[Fuzzer.scala 68:20]
  wire  rnoise_data_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [31:0] rnoise_data_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  rnoise_resp_nm_clock; // @[Fuzzer.scala 68:20]
  wire  rnoise_resp_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [1:0] rnoise_resp_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  rnoise_last_nm_clock; // @[Fuzzer.scala 68:20]
  wire  rnoise_last_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  rnoise_last_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  bnoise_id_nm_clock; // @[Fuzzer.scala 68:20]
  wire  bnoise_id_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  bnoise_id_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  bnoise_resp_nm_clock; // @[Fuzzer.scala 68:20]
  wire  bnoise_resp_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [1:0] bnoise_resp_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  allow_nm_clock; // @[Fuzzer.scala 68:20]
  wire  allow_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [15:0] allow_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  allow_nm_1_clock; // @[Fuzzer.scala 68:20]
  wire  allow_nm_1_io_inc; // @[Fuzzer.scala 68:20]
  wire [15:0] allow_nm_1_io_random; // @[Fuzzer.scala 68:20]
  wire  allow_nm_2_clock; // @[Fuzzer.scala 68:20]
  wire  allow_nm_2_io_inc; // @[Fuzzer.scala 68:20]
  wire [15:0] allow_nm_2_io_random; // @[Fuzzer.scala 68:20]
  wire  allow_nm_3_clock; // @[Fuzzer.scala 68:20]
  wire  allow_nm_3_io_inc; // @[Fuzzer.scala 68:20]
  wire [15:0] allow_nm_3_io_random; // @[Fuzzer.scala 68:20]
  wire  allow_nm_4_clock; // @[Fuzzer.scala 68:20]
  wire  allow_nm_4_io_inc; // @[Fuzzer.scala 68:20]
  wire [15:0] allow_nm_4_io_random; // @[Fuzzer.scala 68:20]
  wire  wnoise_last = wnoise_last_nm_io_random; // @[Delayer.scala 55:39]
  wire  rnoise_last = rnoise_last_nm_io_random; // @[Delayer.scala 60:39]
  reg  hold; // @[Delayer.scala 20:25]
  wire  allow = hold | 16'h3fff <= allow_nm_io_random; // @[Delayer.scala 24:24]
  wire  bundleOut_0_ar_valid = auto_in_ar_valid & allow; // @[Delayer.scala 25:34]
  wire  _GEN_0 = bundleOut_0_ar_valid | hold; // @[Delayer.scala 20:25 21:{26,33}]
  wire  _T = auto_out_ar_ready & bundleOut_0_ar_valid; // @[Decoupled.scala 52:35]
  wire  arnoise_id = arnoise_id_nm_io_random; // @[Delayer.scala 32:18 44:25]
  wire [11:0] arnoise_addr = arnoise_addr_nm_io_random; // @[Delayer.scala 33:18 44:25]
  wire [7:0] arnoise_len = arnoise_len_nm_io_random; // @[Delayer.scala 34:18 44:25]
  wire [2:0] arnoise_size = arnoise_size_nm_io_random; // @[Delayer.scala 35:18 44:25]
  wire [1:0] arnoise_burst = arnoise_burst_nm_io_random; // @[Delayer.scala 36:18 44:25]
  reg  hold_1; // @[Delayer.scala 20:25]
  wire  allow_1 = hold_1 | 16'h3fff <= allow_nm_1_io_random; // @[Delayer.scala 24:24]
  wire  bundleOut_0_aw_valid = auto_in_aw_valid & allow_1; // @[Delayer.scala 25:34]
  wire  _GEN_13 = bundleOut_0_aw_valid | hold_1; // @[Delayer.scala 20:25 21:{26,33}]
  wire  _T_2 = auto_out_aw_ready & bundleOut_0_aw_valid; // @[Decoupled.scala 52:35]
  wire  awnoise_id = awnoise_id_nm_io_random; // @[Delayer.scala 32:18 45:25]
  wire [11:0] awnoise_addr = awnoise_addr_nm_io_random; // @[Delayer.scala 33:18 45:25]
  wire [7:0] awnoise_len = awnoise_len_nm_io_random; // @[Delayer.scala 34:18 45:25]
  wire [2:0] awnoise_size = awnoise_size_nm_io_random; // @[Delayer.scala 35:18 45:25]
  wire [1:0] awnoise_burst = awnoise_burst_nm_io_random; // @[Delayer.scala 36:18 45:25]
  reg  hold_2; // @[Delayer.scala 20:25]
  wire  allow_2 = hold_2 | 16'h3fff <= allow_nm_2_io_random; // @[Delayer.scala 24:24]
  wire  bundleOut_0_w_valid = auto_in_w_valid & allow_2; // @[Delayer.scala 25:34]
  wire  _GEN_26 = bundleOut_0_w_valid | hold_2; // @[Delayer.scala 20:25 21:{26,33}]
  wire  _T_4 = auto_out_w_ready & bundleOut_0_w_valid; // @[Decoupled.scala 52:35]
  wire [31:0] wnoise_data = wnoise_data_nm_io_random; // @[Delayer.scala 46:25 53:19]
  wire [3:0] wnoise_strb = wnoise_strb_nm_io_random; // @[Delayer.scala 46:25 54:19]
  reg  hold_3; // @[Delayer.scala 20:25]
  wire  allow_3 = hold_3 | 16'h3fff <= allow_nm_3_io_random; // @[Delayer.scala 24:24]
  wire  bundleIn_0_b_valid = auto_out_b_valid & allow_3; // @[Delayer.scala 25:34]
  wire  _GEN_32 = bundleIn_0_b_valid | hold_3; // @[Delayer.scala 20:25 21:{26,33}]
  wire  _T_6 = auto_in_b_ready & bundleIn_0_b_valid; // @[Decoupled.scala 52:35]
  wire  bnoise_id = bnoise_id_nm_io_random; // @[Delayer.scala 48:25 62:19]
  wire [1:0] bnoise_resp = bnoise_resp_nm_io_random; // @[Delayer.scala 48:25 63:19]
  reg  hold_4; // @[Delayer.scala 20:25]
  wire  allow_4 = hold_4 | 16'h3fff <= allow_nm_4_io_random; // @[Delayer.scala 24:24]
  wire  bundleIn_0_r_valid = auto_out_r_valid & allow_4; // @[Delayer.scala 25:34]
  wire  _GEN_38 = bundleIn_0_r_valid | hold_4; // @[Delayer.scala 20:25 21:{26,33}]
  wire  _T_8 = auto_in_r_ready & bundleIn_0_r_valid; // @[Decoupled.scala 52:35]
  wire  rnoise_id = rnoise_id_nm_io_random; // @[Delayer.scala 47:25 57:19]
  wire [31:0] rnoise_data = rnoise_data_nm_io_random; // @[Delayer.scala 47:25 58:19]
  wire [1:0] rnoise_resp = rnoise_resp_nm_io_random; // @[Delayer.scala 47:25 59:19]
  LFSRNoiseMaker arnoise_id_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_id_nm_clock),
    .io_inc(arnoise_id_nm_io_inc),
    .io_random(arnoise_id_nm_io_random)
  );
  LFSRNoiseMaker_1 arnoise_addr_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_addr_nm_clock),
    .io_inc(arnoise_addr_nm_io_inc),
    .io_random(arnoise_addr_nm_io_random)
  );
  LFSRNoiseMaker_2 arnoise_len_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_len_nm_clock),
    .io_random(arnoise_len_nm_io_random)
  );
  LFSRNoiseMaker_3 arnoise_size_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_size_nm_clock),
    .io_inc(arnoise_size_nm_io_inc),
    .io_random(arnoise_size_nm_io_random)
  );
  LFSRNoiseMaker_4 arnoise_burst_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_burst_nm_clock),
    .io_inc(arnoise_burst_nm_io_inc),
    .io_random(arnoise_burst_nm_io_random)
  );
  LFSRNoiseMaker arnoise_lock_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_lock_nm_clock),
    .io_inc(arnoise_lock_nm_io_inc),
    .io_random(arnoise_lock_nm_io_random)
  );
  LFSRNoiseMaker_6 arnoise_cache_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_cache_nm_clock),
    .io_inc(arnoise_cache_nm_io_inc),
    .io_random(arnoise_cache_nm_io_random)
  );
  LFSRNoiseMaker_3 arnoise_prot_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_prot_nm_clock),
    .io_inc(arnoise_prot_nm_io_inc),
    .io_random(arnoise_prot_nm_io_random)
  );
  LFSRNoiseMaker_6 arnoise_qos_nm ( // @[Fuzzer.scala 68:20]
    .clock(arnoise_qos_nm_clock),
    .io_inc(arnoise_qos_nm_io_inc),
    .io_random(arnoise_qos_nm_io_random)
  );
  LFSRNoiseMaker awnoise_id_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_id_nm_clock),
    .io_inc(awnoise_id_nm_io_inc),
    .io_random(awnoise_id_nm_io_random)
  );
  LFSRNoiseMaker_1 awnoise_addr_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_addr_nm_clock),
    .io_inc(awnoise_addr_nm_io_inc),
    .io_random(awnoise_addr_nm_io_random)
  );
  LFSRNoiseMaker_2 awnoise_len_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_len_nm_clock),
    .io_random(awnoise_len_nm_io_random)
  );
  LFSRNoiseMaker_3 awnoise_size_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_size_nm_clock),
    .io_inc(awnoise_size_nm_io_inc),
    .io_random(awnoise_size_nm_io_random)
  );
  LFSRNoiseMaker_4 awnoise_burst_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_burst_nm_clock),
    .io_inc(awnoise_burst_nm_io_inc),
    .io_random(awnoise_burst_nm_io_random)
  );
  LFSRNoiseMaker awnoise_lock_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_lock_nm_clock),
    .io_inc(awnoise_lock_nm_io_inc),
    .io_random(awnoise_lock_nm_io_random)
  );
  LFSRNoiseMaker_6 awnoise_cache_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_cache_nm_clock),
    .io_inc(awnoise_cache_nm_io_inc),
    .io_random(awnoise_cache_nm_io_random)
  );
  LFSRNoiseMaker_3 awnoise_prot_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_prot_nm_clock),
    .io_inc(awnoise_prot_nm_io_inc),
    .io_random(awnoise_prot_nm_io_random)
  );
  LFSRNoiseMaker_6 awnoise_qos_nm ( // @[Fuzzer.scala 68:20]
    .clock(awnoise_qos_nm_clock),
    .io_inc(awnoise_qos_nm_io_inc),
    .io_random(awnoise_qos_nm_io_random)
  );
  LFSRNoiseMaker_18 wnoise_data_nm ( // @[Fuzzer.scala 68:20]
    .clock(wnoise_data_nm_clock),
    .io_inc(wnoise_data_nm_io_inc),
    .io_random(wnoise_data_nm_io_random)
  );
  LFSRNoiseMaker_6 wnoise_strb_nm ( // @[Fuzzer.scala 68:20]
    .clock(wnoise_strb_nm_clock),
    .io_inc(wnoise_strb_nm_io_inc),
    .io_random(wnoise_strb_nm_io_random)
  );
  LFSRNoiseMaker wnoise_last_nm ( // @[Fuzzer.scala 68:20]
    .clock(wnoise_last_nm_clock),
    .io_inc(wnoise_last_nm_io_inc),
    .io_random(wnoise_last_nm_io_random)
  );
  LFSRNoiseMaker rnoise_id_nm ( // @[Fuzzer.scala 68:20]
    .clock(rnoise_id_nm_clock),
    .io_inc(rnoise_id_nm_io_inc),
    .io_random(rnoise_id_nm_io_random)
  );
  LFSRNoiseMaker_18 rnoise_data_nm ( // @[Fuzzer.scala 68:20]
    .clock(rnoise_data_nm_clock),
    .io_inc(rnoise_data_nm_io_inc),
    .io_random(rnoise_data_nm_io_random)
  );
  LFSRNoiseMaker_4 rnoise_resp_nm ( // @[Fuzzer.scala 68:20]
    .clock(rnoise_resp_nm_clock),
    .io_inc(rnoise_resp_nm_io_inc),
    .io_random(rnoise_resp_nm_io_random)
  );
  LFSRNoiseMaker rnoise_last_nm ( // @[Fuzzer.scala 68:20]
    .clock(rnoise_last_nm_clock),
    .io_inc(rnoise_last_nm_io_inc),
    .io_random(rnoise_last_nm_io_random)
  );
  LFSRNoiseMaker bnoise_id_nm ( // @[Fuzzer.scala 68:20]
    .clock(bnoise_id_nm_clock),
    .io_inc(bnoise_id_nm_io_inc),
    .io_random(bnoise_id_nm_io_random)
  );
  LFSRNoiseMaker_4 bnoise_resp_nm ( // @[Fuzzer.scala 68:20]
    .clock(bnoise_resp_nm_clock),
    .io_inc(bnoise_resp_nm_io_inc),
    .io_random(bnoise_resp_nm_io_random)
  );
  LFSRNoiseMaker_27 allow_nm ( // @[Fuzzer.scala 68:20]
    .clock(allow_nm_clock),
    .io_inc(allow_nm_io_inc),
    .io_random(allow_nm_io_random)
  );
  LFSRNoiseMaker_27 allow_nm_1 ( // @[Fuzzer.scala 68:20]
    .clock(allow_nm_1_clock),
    .io_inc(allow_nm_1_io_inc),
    .io_random(allow_nm_1_io_random)
  );
  LFSRNoiseMaker_27 allow_nm_2 ( // @[Fuzzer.scala 68:20]
    .clock(allow_nm_2_clock),
    .io_inc(allow_nm_2_io_inc),
    .io_random(allow_nm_2_io_random)
  );
  LFSRNoiseMaker_27 allow_nm_3 ( // @[Fuzzer.scala 68:20]
    .clock(allow_nm_3_clock),
    .io_inc(allow_nm_3_io_inc),
    .io_random(allow_nm_3_io_random)
  );
  LFSRNoiseMaker_27 allow_nm_4 ( // @[Fuzzer.scala 68:20]
    .clock(allow_nm_4_clock),
    .io_inc(allow_nm_4_io_inc),
    .io_random(allow_nm_4_io_random)
  );
  assign auto_in_aw_ready = auto_out_aw_ready & allow_1; // @[Delayer.scala 26:34]
  assign auto_in_w_ready = auto_out_w_ready & allow_2; // @[Delayer.scala 26:34]
  assign auto_in_b_valid = auto_out_b_valid & allow_3; // @[Delayer.scala 25:34]
  assign auto_in_b_bits_id = ~bundleIn_0_b_valid ? bnoise_id : auto_out_b_bits_id; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_b_bits_resp = ~bundleIn_0_b_valid ? bnoise_resp : auto_out_b_bits_resp; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_b_bits_echo_tl_state_size = ~bundleIn_0_b_valid ? 4'h0 : auto_out_b_bits_echo_tl_state_size; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_b_bits_echo_tl_state_source = ~bundleIn_0_b_valid ? 2'h0 : auto_out_b_bits_echo_tl_state_source; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_ar_ready = auto_out_ar_ready & allow; // @[Delayer.scala 26:34]
  assign auto_in_r_valid = auto_out_r_valid & allow_4; // @[Delayer.scala 25:34]
  assign auto_in_r_bits_id = ~bundleIn_0_r_valid ? rnoise_id : auto_out_r_bits_id; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_r_bits_data = ~bundleIn_0_r_valid ? rnoise_data : auto_out_r_bits_data; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_r_bits_resp = ~bundleIn_0_r_valid ? rnoise_resp : auto_out_r_bits_resp; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_r_bits_echo_tl_state_size = ~bundleIn_0_r_valid ? 4'h0 : auto_out_r_bits_echo_tl_state_size; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_r_bits_echo_tl_state_source = ~bundleIn_0_r_valid ? 2'h0 : auto_out_r_bits_echo_tl_state_source; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_in_r_bits_last = ~bundleIn_0_r_valid ? rnoise_last : auto_out_r_bits_last; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_aw_valid = auto_in_aw_valid & allow_1; // @[Delayer.scala 25:34]
  assign auto_out_aw_bits_id = ~bundleOut_0_aw_valid ? awnoise_id : auto_in_aw_bits_id; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_aw_bits_addr = ~bundleOut_0_aw_valid ? awnoise_addr : auto_in_aw_bits_addr; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_aw_bits_len = ~bundleOut_0_aw_valid ? awnoise_len : auto_in_aw_bits_len; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_aw_bits_size = ~bundleOut_0_aw_valid ? awnoise_size : auto_in_aw_bits_size; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_aw_bits_burst = ~bundleOut_0_aw_valid ? awnoise_burst : auto_in_aw_bits_burst; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_aw_bits_echo_tl_state_size = ~bundleOut_0_aw_valid ? 4'h0 : auto_in_aw_bits_echo_tl_state_size; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_aw_bits_echo_tl_state_source = ~bundleOut_0_aw_valid ? 2'h0 : auto_in_aw_bits_echo_tl_state_source; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_w_valid = auto_in_w_valid & allow_2; // @[Delayer.scala 25:34]
  assign auto_out_w_bits_data = ~bundleOut_0_w_valid ? wnoise_data : auto_in_w_bits_data; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_w_bits_strb = ~bundleOut_0_w_valid ? wnoise_strb : auto_in_w_bits_strb; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_w_bits_last = ~bundleOut_0_w_valid ? wnoise_last : auto_in_w_bits_last; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_b_ready = auto_in_b_ready & allow_3; // @[Delayer.scala 26:34]
  assign auto_out_ar_valid = auto_in_ar_valid & allow; // @[Delayer.scala 25:34]
  assign auto_out_ar_bits_id = ~bundleOut_0_ar_valid ? arnoise_id : auto_in_ar_bits_id; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_ar_bits_addr = ~bundleOut_0_ar_valid ? arnoise_addr : auto_in_ar_bits_addr; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_ar_bits_len = ~bundleOut_0_ar_valid ? arnoise_len : auto_in_ar_bits_len; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_ar_bits_size = ~bundleOut_0_ar_valid ? arnoise_size : auto_in_ar_bits_size; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_ar_bits_burst = ~bundleOut_0_ar_valid ? arnoise_burst : auto_in_ar_bits_burst; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_ar_bits_echo_tl_state_size = ~bundleOut_0_ar_valid ? 4'h0 : auto_in_ar_bits_echo_tl_state_size; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_ar_bits_echo_tl_state_source = ~bundleOut_0_ar_valid ? 2'h0 : auto_in_ar_bits_echo_tl_state_source; // @[Delayer.scala 27:17 28:{26,38}]
  assign auto_out_r_ready = auto_in_r_ready & allow_4; // @[Delayer.scala 26:34]
  assign arnoise_id_nm_clock = clock;
  assign arnoise_id_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign arnoise_addr_nm_clock = clock;
  assign arnoise_addr_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign arnoise_len_nm_clock = clock;
  assign arnoise_size_nm_clock = clock;
  assign arnoise_size_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign arnoise_burst_nm_clock = clock;
  assign arnoise_burst_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign arnoise_lock_nm_clock = clock;
  assign arnoise_lock_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign arnoise_cache_nm_clock = clock;
  assign arnoise_cache_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign arnoise_prot_nm_clock = clock;
  assign arnoise_prot_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign arnoise_qos_nm_clock = clock;
  assign arnoise_qos_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign awnoise_id_nm_clock = clock;
  assign awnoise_id_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign awnoise_addr_nm_clock = clock;
  assign awnoise_addr_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign awnoise_len_nm_clock = clock;
  assign awnoise_size_nm_clock = clock;
  assign awnoise_size_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign awnoise_burst_nm_clock = clock;
  assign awnoise_burst_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign awnoise_lock_nm_clock = clock;
  assign awnoise_lock_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign awnoise_cache_nm_clock = clock;
  assign awnoise_cache_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign awnoise_prot_nm_clock = clock;
  assign awnoise_prot_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign awnoise_qos_nm_clock = clock;
  assign awnoise_qos_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign wnoise_data_nm_clock = clock;
  assign wnoise_data_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign wnoise_strb_nm_clock = clock;
  assign wnoise_strb_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign wnoise_last_nm_clock = clock;
  assign wnoise_last_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign rnoise_id_nm_clock = clock;
  assign rnoise_id_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign rnoise_data_nm_clock = clock;
  assign rnoise_data_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign rnoise_resp_nm_clock = clock;
  assign rnoise_resp_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign rnoise_last_nm_clock = clock;
  assign rnoise_last_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign bnoise_id_nm_clock = clock;
  assign bnoise_id_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign bnoise_resp_nm_clock = clock;
  assign bnoise_resp_nm_io_inc = 1'h1; // @[Fuzzer.scala 69:15]
  assign allow_nm_clock = clock;
  assign allow_nm_io_inc = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign allow_nm_1_clock = clock;
  assign allow_nm_1_io_inc = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign allow_nm_2_clock = clock;
  assign allow_nm_2_io_inc = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign allow_nm_3_clock = clock;
  assign allow_nm_3_io_inc = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign allow_nm_4_clock = clock;
  assign allow_nm_4_io_inc = auto_out_r_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Delayer.scala 20:25]
      hold <= 1'h0; // @[Delayer.scala 20:25]
    end else if (_T) begin // @[Delayer.scala 22:26]
      hold <= 1'h0; // @[Delayer.scala 22:33]
    end else begin
      hold <= _GEN_0;
    end
    if (reset) begin // @[Delayer.scala 20:25]
      hold_1 <= 1'h0; // @[Delayer.scala 20:25]
    end else if (_T_2) begin // @[Delayer.scala 22:26]
      hold_1 <= 1'h0; // @[Delayer.scala 22:33]
    end else begin
      hold_1 <= _GEN_13;
    end
    if (reset) begin // @[Delayer.scala 20:25]
      hold_2 <= 1'h0; // @[Delayer.scala 20:25]
    end else if (_T_4) begin // @[Delayer.scala 22:26]
      hold_2 <= 1'h0; // @[Delayer.scala 22:33]
    end else begin
      hold_2 <= _GEN_26;
    end
    if (reset) begin // @[Delayer.scala 20:25]
      hold_3 <= 1'h0; // @[Delayer.scala 20:25]
    end else if (_T_6) begin // @[Delayer.scala 22:26]
      hold_3 <= 1'h0; // @[Delayer.scala 22:33]
    end else begin
      hold_3 <= _GEN_32;
    end
    if (reset) begin // @[Delayer.scala 20:25]
      hold_4 <= 1'h0; // @[Delayer.scala 20:25]
    end else if (_T_8) begin // @[Delayer.scala 22:26]
      hold_4 <= 1'h0; // @[Delayer.scala 22:33]
    end else begin
      hold_4 <= _GEN_38;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  hold = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  hold_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  hold_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  hold_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  hold_4 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IDMapGenerator(
  input        clock,
  input        reset,
  output       io_free_ready,
  input        io_free_valid,
  input  [1:0] io_free_bits,
  input        io_alloc_ready,
  output       io_alloc_valid,
  output [1:0] io_alloc_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [3:0] bitmap; // @[Fuzzer.scala 22:23]
  wire [4:0] _select_T = {bitmap, 1'h0}; // @[package.scala 244:48]
  wire [3:0] _select_T_2 = bitmap | _select_T[3:0]; // @[package.scala 244:43]
  wire [5:0] _select_T_3 = {_select_T_2, 2'h0}; // @[package.scala 244:48]
  wire [3:0] _select_T_5 = _select_T_2 | _select_T_3[3:0]; // @[package.scala 244:43]
  wire [4:0] _select_T_7 = {_select_T_5, 1'h0}; // @[Fuzzer.scala 24:33]
  wire [4:0] _select_T_8 = ~_select_T_7; // @[Fuzzer.scala 24:16]
  wire [4:0] _GEN_2 = {{1'd0}, bitmap}; // @[Fuzzer.scala 24:39]
  wire [4:0] select = _select_T_8 & _GEN_2; // @[Fuzzer.scala 24:39]
  wire  io_alloc_bits_hi = select[4]; // @[OneHot.scala 30:18]
  wire [3:0] io_alloc_bits_lo = select[3:0]; // @[OneHot.scala 31:18]
  wire  _io_alloc_bits_T = |io_alloc_bits_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_3 = {{3'd0}, io_alloc_bits_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _io_alloc_bits_T_1 = _GEN_3 | io_alloc_bits_lo; // @[OneHot.scala 32:28]
  wire [1:0] io_alloc_bits_hi_1 = _io_alloc_bits_T_1[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] io_alloc_bits_lo_1 = _io_alloc_bits_T_1[1:0]; // @[OneHot.scala 31:18]
  wire  _io_alloc_bits_T_2 = |io_alloc_bits_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _io_alloc_bits_T_3 = io_alloc_bits_hi_1 | io_alloc_bits_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] _io_alloc_bits_T_6 = {_io_alloc_bits_T,_io_alloc_bits_T_2,_io_alloc_bits_T_3[1]}; // @[Cat.scala 33:92]
  wire  _T = io_alloc_ready & io_alloc_valid; // @[Decoupled.scala 52:35]
  wire [3:0] _clr_T = 4'h1 << io_alloc_bits; // @[OneHot.scala 57:35]
  wire [3:0] clr = _T ? _clr_T : 4'h0; // @[Fuzzer.scala 29:{26,32}]
  wire  _T_1 = io_free_ready & io_free_valid; // @[Decoupled.scala 52:35]
  wire [3:0] _set_T = 4'h1 << io_free_bits; // @[OneHot.scala 57:35]
  wire [3:0] set = _T_1 ? _set_T : 4'h0; // @[Fuzzer.scala 32:{25,31}]
  wire [3:0] _bitmap_T = ~clr; // @[Fuzzer.scala 34:23]
  wire [3:0] _bitmap_T_1 = bitmap & _bitmap_T; // @[Fuzzer.scala 34:21]
  wire [3:0] _bitmap_T_2 = _bitmap_T_1 | set; // @[Fuzzer.scala 34:29]
  wire [3:0] _T_5 = _bitmap_T_1 >> io_free_bits; // @[Fuzzer.scala 35:45]
  assign io_free_ready = 1'h1; // @[Fuzzer.scala 19:17]
  assign io_alloc_valid = |bitmap; // @[Fuzzer.scala 26:31]
  assign io_alloc_bits = _io_alloc_bits_T_6[1:0]; // @[Fuzzer.scala 25:17]
  always @(posedge clock) begin
    if (reset) begin // @[Fuzzer.scala 22:23]
      bitmap <= 4'hf; // @[Fuzzer.scala 22:23]
    end else begin
      bitmap <= _bitmap_T_2; // @[Fuzzer.scala 34:10]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_free_valid | ~_T_5[0])) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fuzzer.scala:35 assert (!io.free.valid || !(bitmap & ~clr)(io.free.bits)) // No double freeing\n"
            ); // @[Fuzzer.scala 35:10]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_free_valid | ~_T_5[0]) & ~reset) begin
          $fatal; // @[Fuzzer.scala 35:10]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  bitmap = _RAND_0[3:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LFSRNoiseMaker_36(
  input         clock,
  input         io_inc,
  output [10:0] io_random
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] lfsrs_0; // @[Fuzzer.scala 43:19]
  wire  lfsrs_xor = lfsrs_0[0] ^ lfsrs_0[1] ^ lfsrs_0[3] ^ lfsrs_0[4]; // @[Fuzzer.scala 44:43]
  wire [63:0] _lfsrs_lfsr_T_2 = {lfsrs_xor,lfsrs_0[63:1]}; // @[Cat.scala 33:92]
  assign io_random = lfsrs_0[10:0]; // @[Fuzzer.scala 63:26]
  always @(posedge clock) begin
    if (io_inc) begin // @[Fuzzer.scala 45:22]
      if (lfsrs_0 == 64'h0) begin // @[Fuzzer.scala 46:18]
        lfsrs_0 <= 64'h1;
      end else begin
        lfsrs_0 <= _lfsrs_lfsr_T_2;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  lfsrs_0 = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFuzzer(
  input         clock,
  input         reset,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [10:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  output        io_finished
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  idMap_clock; // @[Fuzzer.scala 143:23]
  wire  idMap_reset; // @[Fuzzer.scala 143:23]
  wire  idMap_io_free_ready; // @[Fuzzer.scala 143:23]
  wire  idMap_io_free_valid; // @[Fuzzer.scala 143:23]
  wire [1:0] idMap_io_free_bits; // @[Fuzzer.scala 143:23]
  wire  idMap_io_alloc_ready; // @[Fuzzer.scala 143:23]
  wire  idMap_io_alloc_valid; // @[Fuzzer.scala 143:23]
  wire [1:0] idMap_io_alloc_bits; // @[Fuzzer.scala 143:23]
  wire  arth_op_3_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arth_op_3_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [2:0] arth_op_3_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  log_op_nm_clock; // @[Fuzzer.scala 68:20]
  wire  log_op_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [1:0] log_op_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  amo_size_nm_clock; // @[Fuzzer.scala 68:20]
  wire  amo_size_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  amo_size_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  size_nm_clock; // @[Fuzzer.scala 68:20]
  wire  size_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] size_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  rawAddr_nm_clock; // @[Fuzzer.scala 68:20]
  wire  rawAddr_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [10:0] rawAddr_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  mask_nm_clock; // @[Fuzzer.scala 68:20]
  wire  mask_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] mask_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  data_nm_clock; // @[Fuzzer.scala 68:20]
  wire  data_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [31:0] data_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  a_type_sel_nm_clock; // @[Fuzzer.scala 68:20]
  wire  a_type_sel_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [2:0] a_type_sel_nm_io_random; // @[Fuzzer.scala 68:20]
  reg [12:0] num_reqs; // @[Fuzzer.scala 127:23]
  reg [12:0] num_resps; // @[Fuzzer.scala 128:24]
  wire  a_gen = num_reqs != 13'h0; // @[Fuzzer.scala 198:45]
  wire [25:0] _addr_T_1 = 26'h7ff << size_nm_io_random; // @[package.scala 234:77]
  wire [10:0] _addr_T_3 = ~_addr_T_1[10:0]; // @[package.scala 234:46]
  wire [10:0] _addr_T_4 = ~_addr_T_3; // @[Fuzzer.scala 154:83]
  wire [10:0] addr = rawAddr_nm_io_random & _addr_T_4; // @[Fuzzer.scala 154:81]
  wire [11:0] _legal_dest_T_1 = {1'b0,$signed(addr)}; // @[Parameters.scala 137:49]
  wire [11:0] _legal_dest_T_3 = $signed(_legal_dest_T_1) & 12'sh800; // @[Parameters.scala 137:52]
  wire  _legal_dest_T_4 = $signed(_legal_dest_T_3) == 12'sh0; // @[Parameters.scala 137:67]
  wire  alegal = size_nm_io_random <= 4'ha; // @[Parameters.scala 92:42]
  wire  _legal_T_41 = 3'h1 == a_type_sel_nm_io_random ? alegal : alegal; // @[Mux.scala 81:58]
  wire  _legal_T_43 = 3'h2 == a_type_sel_nm_io_random ? alegal : _legal_T_41; // @[Mux.scala 81:58]
  wire  _legal_T_45 = 3'h3 == a_type_sel_nm_io_random ? alegal : _legal_T_43; // @[Mux.scala 81:58]
  wire  _legal_T_47 = 3'h4 == a_type_sel_nm_io_random ? alegal : _legal_T_45; // @[Mux.scala 81:58]
  wire  _legal_T_49 = 3'h5 == a_type_sel_nm_io_random ? alegal : _legal_T_47; // @[Mux.scala 81:58]
  wire  legal = _legal_dest_T_4 & _legal_T_49; // @[Fuzzer.scala 181:28]
  reg [7:0] counter; // @[Edges.scala 228:27]
  wire  a_first = counter == 8'h0; // @[Edges.scala 230:25]
  wire  out_a_valid = ~reset & a_gen & legal & (~a_first | idMap_io_alloc_valid); // @[Fuzzer.scala 199:45]
  wire  _T = auto_out_a_ready & out_a_valid; // @[Decoupled.scala 52:35]
  wire [3:0] abits_size = size_nm_io_random; // @[Edges.scala 447:17 450:15]
  wire [3:0] _bits_T_3_size = 3'h1 == a_type_sel_nm_io_random ? abits_size : abits_size; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_5_size = 3'h2 == a_type_sel_nm_io_random ? abits_size : _bits_T_3_size; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_7_size = 3'h3 == a_type_sel_nm_io_random ? abits_size : _bits_T_5_size; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_9_size = 3'h4 == a_type_sel_nm_io_random ? abits_size : _bits_T_7_size; // @[Mux.scala 81:58]
  wire [3:0] bits_size = 3'h5 == a_type_sel_nm_io_random ? abits_size : _bits_T_9_size; // @[Mux.scala 81:58]
  wire [24:0] _beats1_decode_T_1 = 25'h3ff << bits_size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode = _beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire [2:0] _bits_T_3_opcode = 3'h1 == a_type_sel_nm_io_random ? 3'h0 : 3'h4; // @[Mux.scala 81:58]
  wire [2:0] _bits_T_5_opcode = 3'h2 == a_type_sel_nm_io_random ? 3'h1 : _bits_T_3_opcode; // @[Mux.scala 81:58]
  wire [2:0] _bits_T_7_opcode = 3'h3 == a_type_sel_nm_io_random ? 3'h4 : _bits_T_5_opcode; // @[Mux.scala 81:58]
  wire [2:0] _bits_T_9_opcode = 3'h4 == a_type_sel_nm_io_random ? 3'h4 : _bits_T_7_opcode; // @[Mux.scala 81:58]
  wire [2:0] bits_opcode = 3'h5 == a_type_sel_nm_io_random ? 3'h4 : _bits_T_9_opcode; // @[Mux.scala 81:58]
  wire  beats1_opdata = ~bits_opcode[2]; // @[Edges.scala 91:28]
  wire [7:0] beats1 = beats1_opdata ? beats1_decode : 8'h0; // @[Edges.scala 220:14]
  wire [7:0] counter1 = counter - 8'h1; // @[Edges.scala 229:28]
  wire  a_last = counter == 8'h1 | beats1 == 8'h0; // @[Edges.scala 231:37]
  wire  req_done = a_last & _T; // @[Edges.scala 232:22]
  wire [24:0] _beats1_decode_T_5 = 25'h3ff << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_7 = ~_beats1_decode_T_5[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode_1 = _beats1_decode_T_7[9:2]; // @[Edges.scala 219:59]
  wire  beats1_opdata_1 = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [7:0] beats1_1 = beats1_opdata_1 ? beats1_decode_1 : 8'h0; // @[Edges.scala 220:14]
  reg [7:0] counter_1; // @[Edges.scala 228:27]
  wire [7:0] counter1_1 = counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first = counter_1 == 8'h0; // @[Edges.scala 230:25]
  wire  d_last = counter_1 == 8'h1 | beats1_1 == 8'h0; // @[Edges.scala 231:37]
  reg [1:0] src_r; // @[Reg.scala 19:16]
  wire  mask_sizeOH_shiftAmount = abits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = size_nm_io_random >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = addr[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = addr[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] _mask_T_1 = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 33:92]
  wire [3:0] mask = mask_nm_io_random & _mask_T_1; // @[Fuzzer.scala 155:56]
  wire [3:0] _bits_T_3_mask = 3'h1 == a_type_sel_nm_io_random ? _mask_T_1 : _mask_T_1; // @[Mux.scala 81:58]
  wire [31:0] pfbits_data = data_nm_io_random; // @[Edges.scala 465:17 472:15]
  wire [31:0] _bits_T_3_data = 3'h1 == a_type_sel_nm_io_random ? pfbits_data : 32'h0; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_5_mask = 3'h2 == a_type_sel_nm_io_random ? mask : _bits_T_3_mask; // @[Mux.scala 81:58]
  wire [31:0] _bits_T_5_data = 3'h2 == a_type_sel_nm_io_random ? pfbits_data : _bits_T_3_data; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_7_mask = 3'h3 == a_type_sel_nm_io_random ? _mask_T_1 : _bits_T_5_mask; // @[Mux.scala 81:58]
  wire [31:0] _bits_T_7_data = 3'h3 == a_type_sel_nm_io_random ? 32'h0 : _bits_T_5_data; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_9_mask = 3'h4 == a_type_sel_nm_io_random ? _mask_T_1 : _bits_T_7_mask; // @[Mux.scala 81:58]
  wire [31:0] _bits_T_9_data = 3'h4 == a_type_sel_nm_io_random ? 32'h0 : _bits_T_7_data; // @[Mux.scala 81:58]
  wire  _inc_T = ~legal; // @[Fuzzer.scala 211:12]
  wire [12:0] _num_reqs_T_1 = num_reqs - 13'h1; // @[Fuzzer.scala 216:30]
  wire [12:0] _num_resps_T_1 = num_resps - 13'h1; // @[Fuzzer.scala 220:32]
  IDMapGenerator idMap ( // @[Fuzzer.scala 143:23]
    .clock(idMap_clock),
    .reset(idMap_reset),
    .io_free_ready(idMap_io_free_ready),
    .io_free_valid(idMap_io_free_valid),
    .io_free_bits(idMap_io_free_bits),
    .io_alloc_ready(idMap_io_alloc_ready),
    .io_alloc_valid(idMap_io_alloc_valid),
    .io_alloc_bits(idMap_io_alloc_bits)
  );
  LFSRNoiseMaker_3 arth_op_3_nm ( // @[Fuzzer.scala 68:20]
    .clock(arth_op_3_nm_clock),
    .io_inc(arth_op_3_nm_io_inc),
    .io_random(arth_op_3_nm_io_random)
  );
  LFSRNoiseMaker_4 log_op_nm ( // @[Fuzzer.scala 68:20]
    .clock(log_op_nm_clock),
    .io_inc(log_op_nm_io_inc),
    .io_random(log_op_nm_io_random)
  );
  LFSRNoiseMaker amo_size_nm ( // @[Fuzzer.scala 68:20]
    .clock(amo_size_nm_clock),
    .io_inc(amo_size_nm_io_inc),
    .io_random(amo_size_nm_io_random)
  );
  LFSRNoiseMaker_6 size_nm ( // @[Fuzzer.scala 68:20]
    .clock(size_nm_clock),
    .io_inc(size_nm_io_inc),
    .io_random(size_nm_io_random)
  );
  LFSRNoiseMaker_36 rawAddr_nm ( // @[Fuzzer.scala 68:20]
    .clock(rawAddr_nm_clock),
    .io_inc(rawAddr_nm_io_inc),
    .io_random(rawAddr_nm_io_random)
  );
  LFSRNoiseMaker_6 mask_nm ( // @[Fuzzer.scala 68:20]
    .clock(mask_nm_clock),
    .io_inc(mask_nm_io_inc),
    .io_random(mask_nm_io_random)
  );
  LFSRNoiseMaker_18 data_nm ( // @[Fuzzer.scala 68:20]
    .clock(data_nm_clock),
    .io_inc(data_nm_io_inc),
    .io_random(data_nm_io_random)
  );
  LFSRNoiseMaker_3 a_type_sel_nm ( // @[Fuzzer.scala 68:20]
    .clock(a_type_sel_nm_clock),
    .io_inc(a_type_sel_nm_io_inc),
    .io_random(a_type_sel_nm_io_random)
  );
  assign auto_out_a_valid = ~reset & a_gen & legal & (~a_first | idMap_io_alloc_valid); // @[Fuzzer.scala 199:45]
  assign auto_out_a_bits_opcode = 3'h5 == a_type_sel_nm_io_random ? 3'h4 : _bits_T_9_opcode; // @[Mux.scala 81:58]
  assign auto_out_a_bits_size = 3'h5 == a_type_sel_nm_io_random ? abits_size : _bits_T_9_size; // @[Mux.scala 81:58]
  assign auto_out_a_bits_source = a_first ? idMap_io_alloc_bits : src_r; // @[package.scala 79:42]
  assign auto_out_a_bits_address = rawAddr_nm_io_random & _addr_T_4; // @[Fuzzer.scala 154:81]
  assign auto_out_a_bits_mask = 3'h5 == a_type_sel_nm_io_random ? _mask_T_1 : _bits_T_9_mask; // @[Mux.scala 81:58]
  assign auto_out_a_bits_data = 3'h5 == a_type_sel_nm_io_random ? 32'h0 : _bits_T_9_data; // @[Mux.scala 81:58]
  assign io_finished = num_resps == 13'h0; // @[Fuzzer.scala 130:32]
  assign idMap_clock = clock;
  assign idMap_reset = reset;
  assign idMap_io_free_valid = d_first & auto_out_d_valid; // @[Fuzzer.scala 201:36]
  assign idMap_io_free_bits = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign idMap_io_alloc_ready = a_gen & legal & a_first & auto_out_a_ready; // @[Fuzzer.scala 200:55]
  assign arth_op_3_nm_clock = clock;
  assign arth_op_3_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign log_op_nm_clock = clock;
  assign log_op_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign amo_size_nm_clock = clock;
  assign amo_size_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign size_nm_clock = clock;
  assign size_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign rawAddr_nm_clock = clock;
  assign rawAddr_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign mask_nm_clock = clock;
  assign mask_nm_io_inc = _inc_T | _T; // @[Fuzzer.scala 212:24]
  assign data_nm_clock = clock;
  assign data_nm_io_inc = _inc_T | _T; // @[Fuzzer.scala 212:24]
  assign a_type_sel_nm_clock = clock;
  assign a_type_sel_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  always @(posedge clock) begin
    if (reset) begin // @[Fuzzer.scala 127:23]
      num_reqs <= 13'h1388; // @[Fuzzer.scala 127:23]
    end else if (_T & a_last) begin // @[Fuzzer.scala 215:37]
      num_reqs <= _num_reqs_T_1; // @[Fuzzer.scala 216:18]
    end
    if (reset) begin // @[Fuzzer.scala 128:24]
      num_resps <= 13'h1388; // @[Fuzzer.scala 128:24]
    end else if (auto_out_d_valid & d_last) begin // @[Fuzzer.scala 219:37]
      num_resps <= _num_resps_T_1; // @[Fuzzer.scala 220:19]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 8'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (auto_out_d_valid) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata_1) begin // @[Edges.scala 220:14]
          counter_1 <= beats1_decode_1;
        end else begin
          counter_1 <= 8'h0;
        end
      end else begin
        counter_1 <= counter1_1;
      end
    end
    if (a_first) begin // @[Reg.scala 20:18]
      src_r <= idMap_io_alloc_bits; // @[Reg.scala 20:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  num_reqs = _RAND_0[12:0];
  _RAND_1 = {1{`RANDOM}};
  num_resps = _RAND_1[12:0];
  _RAND_2 = {1{`RANDOM}};
  counter = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  counter_1 = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  src_r = _RAND_4[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFuzzer_1(
  input         clock,
  input         reset,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [11:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  output        io_finished
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  idMap_clock; // @[Fuzzer.scala 143:23]
  wire  idMap_reset; // @[Fuzzer.scala 143:23]
  wire  idMap_io_free_ready; // @[Fuzzer.scala 143:23]
  wire  idMap_io_free_valid; // @[Fuzzer.scala 143:23]
  wire [1:0] idMap_io_free_bits; // @[Fuzzer.scala 143:23]
  wire  idMap_io_alloc_ready; // @[Fuzzer.scala 143:23]
  wire  idMap_io_alloc_valid; // @[Fuzzer.scala 143:23]
  wire [1:0] idMap_io_alloc_bits; // @[Fuzzer.scala 143:23]
  wire  arth_op_3_nm_clock; // @[Fuzzer.scala 68:20]
  wire  arth_op_3_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [2:0] arth_op_3_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  log_op_nm_clock; // @[Fuzzer.scala 68:20]
  wire  log_op_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [1:0] log_op_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  amo_size_nm_clock; // @[Fuzzer.scala 68:20]
  wire  amo_size_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire  amo_size_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  size_nm_clock; // @[Fuzzer.scala 68:20]
  wire  size_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] size_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  rawAddr_nm_clock; // @[Fuzzer.scala 68:20]
  wire  rawAddr_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [11:0] rawAddr_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  mask_nm_clock; // @[Fuzzer.scala 68:20]
  wire  mask_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [3:0] mask_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  data_nm_clock; // @[Fuzzer.scala 68:20]
  wire  data_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [31:0] data_nm_io_random; // @[Fuzzer.scala 68:20]
  wire  a_type_sel_nm_clock; // @[Fuzzer.scala 68:20]
  wire  a_type_sel_nm_io_inc; // @[Fuzzer.scala 68:20]
  wire [2:0] a_type_sel_nm_io_random; // @[Fuzzer.scala 68:20]
  reg [12:0] num_reqs; // @[Fuzzer.scala 127:23]
  reg [12:0] num_resps; // @[Fuzzer.scala 128:24]
  wire  a_gen = num_reqs != 13'h0; // @[Fuzzer.scala 198:45]
  wire [26:0] _addr_T_1 = 27'hfff << size_nm_io_random; // @[package.scala 234:77]
  wire [11:0] _addr_T_3 = ~_addr_T_1[11:0]; // @[package.scala 234:46]
  wire [11:0] _addr_T_4 = ~_addr_T_3; // @[Fuzzer.scala 154:83]
  wire [11:0] addr = rawAddr_nm_io_random & _addr_T_4; // @[Fuzzer.scala 154:81]
  wire [11:0] _legal_dest_T = addr ^ 12'h800; // @[Parameters.scala 137:31]
  wire [12:0] _legal_dest_T_1 = {1'b0,$signed(_legal_dest_T)}; // @[Parameters.scala 137:49]
  wire [12:0] _legal_dest_T_3 = $signed(_legal_dest_T_1) & -13'sh800; // @[Parameters.scala 137:52]
  wire  _legal_dest_T_4 = $signed(_legal_dest_T_3) == 13'sh0; // @[Parameters.scala 137:67]
  wire  alegal = size_nm_io_random <= 4'ha; // @[Parameters.scala 92:42]
  wire  _legal_T_41 = 3'h1 == a_type_sel_nm_io_random ? alegal : alegal; // @[Mux.scala 81:58]
  wire  _legal_T_43 = 3'h2 == a_type_sel_nm_io_random ? alegal : _legal_T_41; // @[Mux.scala 81:58]
  wire  _legal_T_45 = 3'h3 == a_type_sel_nm_io_random ? alegal : _legal_T_43; // @[Mux.scala 81:58]
  wire  _legal_T_47 = 3'h4 == a_type_sel_nm_io_random ? alegal : _legal_T_45; // @[Mux.scala 81:58]
  wire  _legal_T_49 = 3'h5 == a_type_sel_nm_io_random ? alegal : _legal_T_47; // @[Mux.scala 81:58]
  wire  legal = _legal_dest_T_4 & _legal_T_49; // @[Fuzzer.scala 181:28]
  reg [7:0] counter; // @[Edges.scala 228:27]
  wire  a_first = counter == 8'h0; // @[Edges.scala 230:25]
  wire  out_a_valid = ~reset & a_gen & legal & (~a_first | idMap_io_alloc_valid); // @[Fuzzer.scala 199:45]
  wire  _T = auto_out_a_ready & out_a_valid; // @[Decoupled.scala 52:35]
  wire [3:0] abits_size = size_nm_io_random; // @[Edges.scala 447:17 450:15]
  wire [3:0] _bits_T_3_size = 3'h1 == a_type_sel_nm_io_random ? abits_size : abits_size; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_5_size = 3'h2 == a_type_sel_nm_io_random ? abits_size : _bits_T_3_size; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_7_size = 3'h3 == a_type_sel_nm_io_random ? abits_size : _bits_T_5_size; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_9_size = 3'h4 == a_type_sel_nm_io_random ? abits_size : _bits_T_7_size; // @[Mux.scala 81:58]
  wire [3:0] bits_size = 3'h5 == a_type_sel_nm_io_random ? abits_size : _bits_T_9_size; // @[Mux.scala 81:58]
  wire [24:0] _beats1_decode_T_1 = 25'h3ff << bits_size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode = _beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire [2:0] _bits_T_3_opcode = 3'h1 == a_type_sel_nm_io_random ? 3'h0 : 3'h4; // @[Mux.scala 81:58]
  wire [2:0] _bits_T_5_opcode = 3'h2 == a_type_sel_nm_io_random ? 3'h1 : _bits_T_3_opcode; // @[Mux.scala 81:58]
  wire [2:0] _bits_T_7_opcode = 3'h3 == a_type_sel_nm_io_random ? 3'h4 : _bits_T_5_opcode; // @[Mux.scala 81:58]
  wire [2:0] _bits_T_9_opcode = 3'h4 == a_type_sel_nm_io_random ? 3'h4 : _bits_T_7_opcode; // @[Mux.scala 81:58]
  wire [2:0] bits_opcode = 3'h5 == a_type_sel_nm_io_random ? 3'h4 : _bits_T_9_opcode; // @[Mux.scala 81:58]
  wire  beats1_opdata = ~bits_opcode[2]; // @[Edges.scala 91:28]
  wire [7:0] beats1 = beats1_opdata ? beats1_decode : 8'h0; // @[Edges.scala 220:14]
  wire [7:0] counter1 = counter - 8'h1; // @[Edges.scala 229:28]
  wire  a_last = counter == 8'h1 | beats1 == 8'h0; // @[Edges.scala 231:37]
  wire  req_done = a_last & _T; // @[Edges.scala 232:22]
  wire [24:0] _beats1_decode_T_5 = 25'h3ff << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_7 = ~_beats1_decode_T_5[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode_1 = _beats1_decode_T_7[9:2]; // @[Edges.scala 219:59]
  wire  beats1_opdata_1 = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [7:0] beats1_1 = beats1_opdata_1 ? beats1_decode_1 : 8'h0; // @[Edges.scala 220:14]
  reg [7:0] counter_1; // @[Edges.scala 228:27]
  wire [7:0] counter1_1 = counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first = counter_1 == 8'h0; // @[Edges.scala 230:25]
  wire  d_last = counter_1 == 8'h1 | beats1_1 == 8'h0; // @[Edges.scala 231:37]
  reg [1:0] src_r; // @[Reg.scala 19:16]
  wire  mask_sizeOH_shiftAmount = abits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = size_nm_io_random >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = addr[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = addr[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] _mask_T_1 = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 33:92]
  wire [3:0] mask = mask_nm_io_random & _mask_T_1; // @[Fuzzer.scala 155:56]
  wire [3:0] _bits_T_3_mask = 3'h1 == a_type_sel_nm_io_random ? _mask_T_1 : _mask_T_1; // @[Mux.scala 81:58]
  wire [31:0] pfbits_data = data_nm_io_random; // @[Edges.scala 465:17 472:15]
  wire [31:0] _bits_T_3_data = 3'h1 == a_type_sel_nm_io_random ? pfbits_data : 32'h0; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_5_mask = 3'h2 == a_type_sel_nm_io_random ? mask : _bits_T_3_mask; // @[Mux.scala 81:58]
  wire [31:0] _bits_T_5_data = 3'h2 == a_type_sel_nm_io_random ? pfbits_data : _bits_T_3_data; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_7_mask = 3'h3 == a_type_sel_nm_io_random ? _mask_T_1 : _bits_T_5_mask; // @[Mux.scala 81:58]
  wire [31:0] _bits_T_7_data = 3'h3 == a_type_sel_nm_io_random ? 32'h0 : _bits_T_5_data; // @[Mux.scala 81:58]
  wire [3:0] _bits_T_9_mask = 3'h4 == a_type_sel_nm_io_random ? _mask_T_1 : _bits_T_7_mask; // @[Mux.scala 81:58]
  wire [31:0] _bits_T_9_data = 3'h4 == a_type_sel_nm_io_random ? 32'h0 : _bits_T_7_data; // @[Mux.scala 81:58]
  wire  _inc_T = ~legal; // @[Fuzzer.scala 211:12]
  wire [12:0] _num_reqs_T_1 = num_reqs - 13'h1; // @[Fuzzer.scala 216:30]
  wire [12:0] _num_resps_T_1 = num_resps - 13'h1; // @[Fuzzer.scala 220:32]
  IDMapGenerator idMap ( // @[Fuzzer.scala 143:23]
    .clock(idMap_clock),
    .reset(idMap_reset),
    .io_free_ready(idMap_io_free_ready),
    .io_free_valid(idMap_io_free_valid),
    .io_free_bits(idMap_io_free_bits),
    .io_alloc_ready(idMap_io_alloc_ready),
    .io_alloc_valid(idMap_io_alloc_valid),
    .io_alloc_bits(idMap_io_alloc_bits)
  );
  LFSRNoiseMaker_3 arth_op_3_nm ( // @[Fuzzer.scala 68:20]
    .clock(arth_op_3_nm_clock),
    .io_inc(arth_op_3_nm_io_inc),
    .io_random(arth_op_3_nm_io_random)
  );
  LFSRNoiseMaker_4 log_op_nm ( // @[Fuzzer.scala 68:20]
    .clock(log_op_nm_clock),
    .io_inc(log_op_nm_io_inc),
    .io_random(log_op_nm_io_random)
  );
  LFSRNoiseMaker amo_size_nm ( // @[Fuzzer.scala 68:20]
    .clock(amo_size_nm_clock),
    .io_inc(amo_size_nm_io_inc),
    .io_random(amo_size_nm_io_random)
  );
  LFSRNoiseMaker_6 size_nm ( // @[Fuzzer.scala 68:20]
    .clock(size_nm_clock),
    .io_inc(size_nm_io_inc),
    .io_random(size_nm_io_random)
  );
  LFSRNoiseMaker_1 rawAddr_nm ( // @[Fuzzer.scala 68:20]
    .clock(rawAddr_nm_clock),
    .io_inc(rawAddr_nm_io_inc),
    .io_random(rawAddr_nm_io_random)
  );
  LFSRNoiseMaker_6 mask_nm ( // @[Fuzzer.scala 68:20]
    .clock(mask_nm_clock),
    .io_inc(mask_nm_io_inc),
    .io_random(mask_nm_io_random)
  );
  LFSRNoiseMaker_18 data_nm ( // @[Fuzzer.scala 68:20]
    .clock(data_nm_clock),
    .io_inc(data_nm_io_inc),
    .io_random(data_nm_io_random)
  );
  LFSRNoiseMaker_3 a_type_sel_nm ( // @[Fuzzer.scala 68:20]
    .clock(a_type_sel_nm_clock),
    .io_inc(a_type_sel_nm_io_inc),
    .io_random(a_type_sel_nm_io_random)
  );
  assign auto_out_a_valid = ~reset & a_gen & legal & (~a_first | idMap_io_alloc_valid); // @[Fuzzer.scala 199:45]
  assign auto_out_a_bits_opcode = 3'h5 == a_type_sel_nm_io_random ? 3'h4 : _bits_T_9_opcode; // @[Mux.scala 81:58]
  assign auto_out_a_bits_size = 3'h5 == a_type_sel_nm_io_random ? abits_size : _bits_T_9_size; // @[Mux.scala 81:58]
  assign auto_out_a_bits_source = a_first ? idMap_io_alloc_bits : src_r; // @[package.scala 79:42]
  assign auto_out_a_bits_address = rawAddr_nm_io_random & _addr_T_4; // @[Fuzzer.scala 154:81]
  assign auto_out_a_bits_mask = 3'h5 == a_type_sel_nm_io_random ? _mask_T_1 : _bits_T_9_mask; // @[Mux.scala 81:58]
  assign auto_out_a_bits_data = 3'h5 == a_type_sel_nm_io_random ? 32'h0 : _bits_T_9_data; // @[Mux.scala 81:58]
  assign io_finished = num_resps == 13'h0; // @[Fuzzer.scala 130:32]
  assign idMap_clock = clock;
  assign idMap_reset = reset;
  assign idMap_io_free_valid = d_first & auto_out_d_valid; // @[Fuzzer.scala 201:36]
  assign idMap_io_free_bits = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign idMap_io_alloc_ready = a_gen & legal & a_first & auto_out_a_ready; // @[Fuzzer.scala 200:55]
  assign arth_op_3_nm_clock = clock;
  assign arth_op_3_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign log_op_nm_clock = clock;
  assign log_op_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign amo_size_nm_clock = clock;
  assign amo_size_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign size_nm_clock = clock;
  assign size_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign rawAddr_nm_clock = clock;
  assign rawAddr_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  assign mask_nm_clock = clock;
  assign mask_nm_io_inc = _inc_T | _T; // @[Fuzzer.scala 212:24]
  assign data_nm_clock = clock;
  assign data_nm_io_inc = _inc_T | _T; // @[Fuzzer.scala 212:24]
  assign a_type_sel_nm_clock = clock;
  assign a_type_sel_nm_io_inc = ~legal | req_done; // @[Fuzzer.scala 211:19]
  always @(posedge clock) begin
    if (reset) begin // @[Fuzzer.scala 127:23]
      num_reqs <= 13'h1388; // @[Fuzzer.scala 127:23]
    end else if (_T & a_last) begin // @[Fuzzer.scala 215:37]
      num_reqs <= _num_reqs_T_1; // @[Fuzzer.scala 216:18]
    end
    if (reset) begin // @[Fuzzer.scala 128:24]
      num_resps <= 13'h1388; // @[Fuzzer.scala 128:24]
    end else if (auto_out_d_valid & d_last) begin // @[Fuzzer.scala 219:37]
      num_resps <= _num_resps_T_1; // @[Fuzzer.scala 220:19]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 8'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (auto_out_d_valid) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata_1) begin // @[Edges.scala 220:14]
          counter_1 <= beats1_decode_1;
        end else begin
          counter_1 <= 8'h0;
        end
      end else begin
        counter_1 <= counter1_1;
      end
    end
    if (a_first) begin // @[Reg.scala 20:18]
      src_r <= idMap_io_alloc_bits; // @[Reg.scala 20:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  num_reqs = _RAND_0[12:0];
  _RAND_1 = {1{`RANDOM}};
  num_resps = _RAND_1[12:0];
  _RAND_2 = {1{`RANDOM}};
  counter = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  counter_1 = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  src_r = _RAND_4[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_13(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [31:0] io_enq_bits_data,
  input  [1:0]  io_enq_bits_resp,
  input  [3:0]  io_enq_bits_echo_tl_state_size,
  input  [1:0]  io_enq_bits_echo_tl_state_source,
  input         io_enq_bits_last,
  input         io_deq_ready,
  output        io_deq_valid,
  output [31:0] io_deq_bits_data,
  output [1:0]  io_deq_bits_resp,
  output [3:0]  io_deq_bits_echo_tl_state_size,
  output [1:0]  io_deq_bits_echo_tl_state_source,
  output        io_deq_bits_last
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] ram_data [0:1023]; // @[Decoupled.scala 275:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [9:0] ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 275:95]
  wire [9:0] ram_data_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_resp [0:1023]; // @[Decoupled.scala 275:95]
  wire  ram_resp_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [9:0] ram_resp_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_resp_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_resp_MPORT_data; // @[Decoupled.scala 275:95]
  wire [9:0] ram_resp_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_resp_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_resp_MPORT_en; // @[Decoupled.scala 275:95]
  reg [3:0] ram_echo_tl_state_size [0:1023]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [9:0] ram_echo_tl_state_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire [9:0] ram_echo_tl_state_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_echo_tl_state_source [0:1023]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [9:0] ram_echo_tl_state_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire [9:0] ram_echo_tl_state_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_last [0:1023]; // @[Decoupled.scala 275:95]
  wire  ram_last_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire [9:0] ram_last_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_last_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_data; // @[Decoupled.scala 275:95]
  wire [9:0] ram_last_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_last_MPORT_en; // @[Decoupled.scala 275:95]
  reg [9:0] enq_ptr_value; // @[Counter.scala 61:40]
  reg [9:0] deq_ptr_value; // @[Counter.scala 61:40]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 279:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 280:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 281:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire [9:0] _value_T_1 = enq_ptr_value + 10'h1; // @[Counter.scala 77:24]
  wire [9:0] _value_T_3 = deq_ptr_value + 10'h1; // @[Counter.scala 77:24]
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = enq_ptr_value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_resp_io_deq_bits_MPORT_en = 1'h1;
  assign ram_resp_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_resp_io_deq_bits_MPORT_data = ram_resp[ram_resp_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_resp_MPORT_data = io_enq_bits_resp;
  assign ram_resp_MPORT_addr = enq_ptr_value;
  assign ram_resp_MPORT_mask = 1'h1;
  assign ram_resp_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_data =
    ram_echo_tl_state_size[ram_echo_tl_state_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_size_MPORT_data = io_enq_bits_echo_tl_state_size;
  assign ram_echo_tl_state_size_MPORT_addr = enq_ptr_value;
  assign ram_echo_tl_state_size_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_data =
    ram_echo_tl_state_source[ram_echo_tl_state_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_source_MPORT_data = io_enq_bits_echo_tl_state_source;
  assign ram_echo_tl_state_source_MPORT_addr = enq_ptr_value;
  assign ram_echo_tl_state_source_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_last_io_deq_bits_MPORT_en = 1'h1;
  assign ram_last_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_last_io_deq_bits_MPORT_data = ram_last[ram_last_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_last_MPORT_data = io_enq_bits_last;
  assign ram_last_MPORT_addr = enq_ptr_value;
  assign ram_last_MPORT_mask = 1'h1;
  assign ram_last_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 304:19]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_resp = ram_resp_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_echo_tl_state_size = ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_echo_tl_state_source = ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  assign io_deq_bits_last = ram_last_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17]
  always @(posedge clock) begin
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_resp_MPORT_en & ram_resp_MPORT_mask) begin
      ram_resp[ram_resp_MPORT_addr] <= ram_resp_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_size_MPORT_en & ram_echo_tl_state_size_MPORT_mask) begin
      ram_echo_tl_state_size[ram_echo_tl_state_size_MPORT_addr] <= ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_source_MPORT_en & ram_echo_tl_state_source_MPORT_mask) begin
      ram_echo_tl_state_source[ram_echo_tl_state_source_MPORT_addr] <= ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_last_MPORT_en & ram_last_MPORT_mask) begin
      ram_last[ram_last_MPORT_addr] <= ram_last_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Counter.scala 61:40]
      enq_ptr_value <= 10'h0; // @[Counter.scala 61:40]
    end else if (do_enq) begin // @[Decoupled.scala 288:16]
      enq_ptr_value <= _value_T_1; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Counter.scala 61:40]
      deq_ptr_value <= 10'h0; // @[Counter.scala 61:40]
    end else if (do_deq) begin // @[Decoupled.scala 292:16]
      deq_ptr_value <= _value_T_3; // @[Counter.scala 77:15]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      maybe_full <= do_enq; // @[Decoupled.scala 296:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    ram_data[initvar] = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    ram_resp[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    ram_echo_tl_state_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    ram_echo_tl_state_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    ram_last[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_5 = {1{`RANDOM}};
  enq_ptr_value = _RAND_5[9:0];
  _RAND_6 = {1{`RANDOM}};
  deq_ptr_value = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  maybe_full = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AXI4Deinterleaver(
  input         clock,
  input         reset,
  output        auto_in_aw_ready,
  input         auto_in_aw_valid,
  input         auto_in_aw_bits_id,
  input  [11:0] auto_in_aw_bits_addr,
  input  [7:0]  auto_in_aw_bits_len,
  input  [2:0]  auto_in_aw_bits_size,
  input  [1:0]  auto_in_aw_bits_burst,
  input  [3:0]  auto_in_aw_bits_echo_tl_state_size,
  input  [1:0]  auto_in_aw_bits_echo_tl_state_source,
  output        auto_in_w_ready,
  input         auto_in_w_valid,
  input  [31:0] auto_in_w_bits_data,
  input  [3:0]  auto_in_w_bits_strb,
  input         auto_in_w_bits_last,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [1:0]  auto_in_b_bits_resp,
  output [3:0]  auto_in_b_bits_echo_tl_state_size,
  output [1:0]  auto_in_b_bits_echo_tl_state_source,
  output        auto_in_ar_ready,
  input         auto_in_ar_valid,
  input         auto_in_ar_bits_id,
  input  [11:0] auto_in_ar_bits_addr,
  input  [7:0]  auto_in_ar_bits_len,
  input  [2:0]  auto_in_ar_bits_size,
  input  [1:0]  auto_in_ar_bits_burst,
  input  [3:0]  auto_in_ar_bits_echo_tl_state_size,
  input  [1:0]  auto_in_ar_bits_echo_tl_state_source,
  input         auto_in_r_ready,
  output        auto_in_r_valid,
  output [31:0] auto_in_r_bits_data,
  output [1:0]  auto_in_r_bits_resp,
  output [3:0]  auto_in_r_bits_echo_tl_state_size,
  output [1:0]  auto_in_r_bits_echo_tl_state_source,
  output        auto_in_r_bits_last,
  input         auto_out_aw_ready,
  output        auto_out_aw_valid,
  output        auto_out_aw_bits_id,
  output [11:0] auto_out_aw_bits_addr,
  output [7:0]  auto_out_aw_bits_len,
  output [2:0]  auto_out_aw_bits_size,
  output [1:0]  auto_out_aw_bits_burst,
  output [3:0]  auto_out_aw_bits_echo_tl_state_size,
  output [1:0]  auto_out_aw_bits_echo_tl_state_source,
  input         auto_out_w_ready,
  output        auto_out_w_valid,
  output [31:0] auto_out_w_bits_data,
  output [3:0]  auto_out_w_bits_strb,
  output        auto_out_w_bits_last,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_resp,
  input  [3:0]  auto_out_b_bits_echo_tl_state_size,
  input  [1:0]  auto_out_b_bits_echo_tl_state_source,
  input         auto_out_ar_ready,
  output        auto_out_ar_valid,
  output        auto_out_ar_bits_id,
  output [11:0] auto_out_ar_bits_addr,
  output [7:0]  auto_out_ar_bits_len,
  output [2:0]  auto_out_ar_bits_size,
  output [1:0]  auto_out_ar_bits_burst,
  output [3:0]  auto_out_ar_bits_echo_tl_state_size,
  output [1:0]  auto_out_ar_bits_echo_tl_state_source,
  output        auto_out_r_ready,
  input         auto_out_r_valid,
  input  [31:0] auto_out_r_bits_data,
  input  [1:0]  auto_out_r_bits_resp,
  input  [3:0]  auto_out_r_bits_echo_tl_state_size,
  input  [1:0]  auto_out_r_bits_echo_tl_state_source,
  input         auto_out_r_bits_last
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  qs_queue_0_clock; // @[Deinterleaver.scala 66:27]
  wire  qs_queue_0_reset; // @[Deinterleaver.scala 66:27]
  wire  qs_queue_0_io_enq_ready; // @[Deinterleaver.scala 66:27]
  wire  qs_queue_0_io_enq_valid; // @[Deinterleaver.scala 66:27]
  wire [31:0] qs_queue_0_io_enq_bits_data; // @[Deinterleaver.scala 66:27]
  wire [1:0] qs_queue_0_io_enq_bits_resp; // @[Deinterleaver.scala 66:27]
  wire [3:0] qs_queue_0_io_enq_bits_echo_tl_state_size; // @[Deinterleaver.scala 66:27]
  wire [1:0] qs_queue_0_io_enq_bits_echo_tl_state_source; // @[Deinterleaver.scala 66:27]
  wire  qs_queue_0_io_enq_bits_last; // @[Deinterleaver.scala 66:27]
  wire  qs_queue_0_io_deq_ready; // @[Deinterleaver.scala 66:27]
  wire  qs_queue_0_io_deq_valid; // @[Deinterleaver.scala 66:27]
  wire [31:0] qs_queue_0_io_deq_bits_data; // @[Deinterleaver.scala 66:27]
  wire [1:0] qs_queue_0_io_deq_bits_resp; // @[Deinterleaver.scala 66:27]
  wire [3:0] qs_queue_0_io_deq_bits_echo_tl_state_size; // @[Deinterleaver.scala 66:27]
  wire [1:0] qs_queue_0_io_deq_bits_echo_tl_state_source; // @[Deinterleaver.scala 66:27]
  wire  qs_queue_0_io_deq_bits_last; // @[Deinterleaver.scala 66:27]
  reg  locked; // @[Deinterleaver.scala 82:29]
  reg [10:0] pending_count; // @[Deinterleaver.scala 92:32]
  wire  enq_readys_0 = qs_queue_0_io_enq_ready; // @[Deinterleaver.scala 125:{33,33}]
  wire  _pending_inc_T = enq_readys_0 & auto_out_r_valid; // @[Decoupled.scala 52:35]
  wire  pending_inc = _pending_inc_T & auto_out_r_bits_last; // @[Deinterleaver.scala 94:49]
  wire  _pending_dec_T = auto_in_r_ready & locked; // @[Decoupled.scala 52:35]
  wire  deq_bits_0_last = qs_queue_0_io_deq_bits_last; // @[Deinterleaver.scala 114:{31,31}]
  wire  pending_dec = _pending_dec_T & deq_bits_0_last; // @[Deinterleaver.scala 95:48]
  wire [10:0] _GEN_1 = {{10'd0}, pending_inc}; // @[Deinterleaver.scala 96:27]
  wire [10:0] _pending_next_T_1 = pending_count + _GEN_1; // @[Deinterleaver.scala 96:27]
  wire [10:0] _GEN_2 = {{10'd0}, pending_dec}; // @[Deinterleaver.scala 96:40]
  wire [10:0] pending_next = _pending_next_T_1 - _GEN_2; // @[Deinterleaver.scala 96:40]
  wire  _pending_T_4 = ~reset; // @[Deinterleaver.scala 99:20]
  wire  pending = pending_next != 11'h0; // @[Deinterleaver.scala 101:18]
  Queue_13 qs_queue_0 ( // @[Deinterleaver.scala 66:27]
    .clock(qs_queue_0_clock),
    .reset(qs_queue_0_reset),
    .io_enq_ready(qs_queue_0_io_enq_ready),
    .io_enq_valid(qs_queue_0_io_enq_valid),
    .io_enq_bits_data(qs_queue_0_io_enq_bits_data),
    .io_enq_bits_resp(qs_queue_0_io_enq_bits_resp),
    .io_enq_bits_echo_tl_state_size(qs_queue_0_io_enq_bits_echo_tl_state_size),
    .io_enq_bits_echo_tl_state_source(qs_queue_0_io_enq_bits_echo_tl_state_source),
    .io_enq_bits_last(qs_queue_0_io_enq_bits_last),
    .io_deq_ready(qs_queue_0_io_deq_ready),
    .io_deq_valid(qs_queue_0_io_deq_valid),
    .io_deq_bits_data(qs_queue_0_io_deq_bits_data),
    .io_deq_bits_resp(qs_queue_0_io_deq_bits_resp),
    .io_deq_bits_echo_tl_state_size(qs_queue_0_io_deq_bits_echo_tl_state_size),
    .io_deq_bits_echo_tl_state_source(qs_queue_0_io_deq_bits_echo_tl_state_source),
    .io_deq_bits_last(qs_queue_0_io_deq_bits_last)
  );
  assign auto_in_aw_ready = auto_out_aw_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_w_ready = auto_out_w_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_valid = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_ar_ready = auto_out_ar_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_r_valid = locked; // @[Deinterleaver.scala 113:20 Nodes.scala 1210:84]
  assign auto_in_r_bits_data = qs_queue_0_io_deq_bits_data; // @[Deinterleaver.scala 114:{31,31}]
  assign auto_in_r_bits_resp = qs_queue_0_io_deq_bits_resp; // @[Deinterleaver.scala 114:{31,31}]
  assign auto_in_r_bits_echo_tl_state_size = qs_queue_0_io_deq_bits_echo_tl_state_size; // @[Deinterleaver.scala 114:{31,31}]
  assign auto_in_r_bits_echo_tl_state_source = qs_queue_0_io_deq_bits_echo_tl_state_source; // @[Deinterleaver.scala 114:{31,31}]
  assign auto_in_r_bits_last = qs_queue_0_io_deq_bits_last; // @[Deinterleaver.scala 114:{31,31}]
  assign auto_out_aw_valid = auto_in_aw_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_w_valid = auto_in_w_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_w_bits_data = auto_in_w_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_w_bits_last = auto_in_w_bits_last; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_ar_valid = auto_in_ar_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_r_ready = qs_queue_0_io_enq_ready; // @[Deinterleaver.scala 125:{33,33}]
  assign qs_queue_0_clock = clock;
  assign qs_queue_0_reset = reset;
  assign qs_queue_0_io_enq_valid = auto_out_r_valid; // @[Deinterleaver.scala 128:28]
  assign qs_queue_0_io_enq_bits_data = auto_out_r_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign qs_queue_0_io_enq_bits_resp = auto_out_r_bits_resp; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign qs_queue_0_io_enq_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign qs_queue_0_io_enq_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign qs_queue_0_io_enq_bits_last = auto_out_r_bits_last; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign qs_queue_0_io_deq_ready = auto_in_r_ready & locked; // @[Decoupled.scala 52:35]
  always @(posedge clock) begin
    if (reset) begin // @[Deinterleaver.scala 82:29]
      locked <= 1'h0; // @[Deinterleaver.scala 82:29]
    end else if (~locked | pending_dec) begin // @[Deinterleaver.scala 107:59]
      locked <= |pending; // @[Deinterleaver.scala 108:18]
    end
    if (reset) begin // @[Deinterleaver.scala 92:32]
      pending_count <= 11'h0; // @[Deinterleaver.scala 92:32]
    end else begin
      pending_count <= pending_next; // @[Deinterleaver.scala 97:19]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~pending_dec | pending_count != 11'h0)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Deinterleaver.scala:99 assert (!dec || count =/= 0.U)\n"); // @[Deinterleaver.scala 99:20]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~pending_dec | pending_count != 11'h0) & ~reset) begin
          $fatal; // @[Deinterleaver.scala 99:20]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_pending_T_4 & ~(~pending_inc | pending_count != 11'h400)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Deinterleaver.scala:100 assert (!inc || count =/= beats.U)\n"); // @[Deinterleaver.scala 100:20]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~pending_inc | pending_count != 11'h400) & _pending_T_4) begin
          $fatal; // @[Deinterleaver.scala 100:20]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  locked = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  pending_count = _RAND_1[10:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [11:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [24:0] _is_aligned_mask_T_1 = 25'h3ff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [9:0] is_aligned_mask = ~_is_aligned_mask_T_1[9:0]; // @[package.scala 234:46]
  wire [11:0] _GEN_62 = {{2'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [11:0] _is_aligned_T = io_in_a_bits_address & _GEN_62; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 33:92]
  wire [12:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_22 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire [12:0] _T_36 = $signed(_T_12) & 13'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 13'sh0; // @[Parameters.scala 137:67]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 4'ha; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _T_22 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_413 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_417 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_469 = _T_417 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire [7:0] a_first_beats1_decode = is_aligned_mask[9:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [7:0] a_first_counter; // @[Edges.scala 228:27]
  wire [7:0] a_first_counter1 = a_first_counter - 8'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 8'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [11:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 52:35]
  wire [24:0] _d_first_beats1_decode_T_1 = 25'h3ff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [9:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [7:0] d_first_counter; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1 = d_first_counter - 8'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 8'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_588 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [3:0] inflight; // @[Monitor.scala 611:27]
  reg [15:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [31:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [7:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [7:0] a_first_counter1_1 = a_first_counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala 230:25]
  reg [7:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1_1 = d_first_counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_64 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_64}; // @[Monitor.scala 634:69]
  wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [31:0] _GEN_71 = {{16'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [31:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_71; // @[Monitor.scala 638:91]
  wire [31:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_597 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_73 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_73}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_328 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_328 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_329 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_329 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [3:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [3:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_330 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_330 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_331 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_331 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] d_clr = _d_first_T & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _d_first_T & d_first_1 & _T_607 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [3:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_75 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [15:0] a_opcodes_set = _GEN_19[15:0];
  wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [15:0] d_opcodes_clr = _GEN_23[15:0];
  wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [31:0] a_sizes_set = _GEN_20[31:0];
  wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [31:0] d_sizes_clr = _GEN_24[31:0];
  wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_1; // @[Monitor.scala 723:35]
  reg [31:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [7:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1_2 = d_first_counter_2 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala 230:25]
  wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [31:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_71; // @[Monitor.scala 747:93]
  wire [31:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala 747:146]
  wire  _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [3:0] d_clr_1 = _d_first_T & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_69 = _d_first_T & d_first_2 & _T_401 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [3:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_714 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [3:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [31:0] d_sizes_clr_1 = _GEN_69[31:0];
  wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [31:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 8'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 8'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 4'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 16'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 32'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 8'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 8'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 4'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 32'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 8'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 8'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_22) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_22 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_469 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_T_469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_469 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_588 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_704[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_704[0] & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_714) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:311:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_714 & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_739) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Xbar.scala:311:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_739 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  size = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  source = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  address = _RAND_4[11:0];
  _RAND_5 = {1{`RANDOM}};
  d_first_counter = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  opcode_1 = _RAND_6[2:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[3:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  denied = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[3:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[15:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[7:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[7:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_15(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [11:0] io_enq_bits_addr,
  input  [7:0]  io_enq_bits_len,
  input  [2:0]  io_enq_bits_size,
  input  [3:0]  io_enq_bits_echo_tl_state_size,
  input  [1:0]  io_enq_bits_echo_tl_state_source,
  input         io_enq_bits_wen,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_id,
  output [11:0] io_deq_bits_addr,
  output [7:0]  io_deq_bits_len,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_burst,
  output [3:0]  io_deq_bits_echo_tl_state_size,
  output [1:0]  io_deq_bits_echo_tl_state_source,
  output        io_deq_bits_wen
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  reg  ram_id [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_id_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_id_MPORT_en; // @[Decoupled.scala 275:95]
  reg [11:0] ram_addr [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_addr_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_addr_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [11:0] ram_addr_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [11:0] ram_addr_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_addr_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_addr_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_addr_MPORT_en; // @[Decoupled.scala 275:95]
  reg [7:0] ram_len [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_len_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_len_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [7:0] ram_len_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [7:0] ram_len_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_len_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_len_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_len_MPORT_en; // @[Decoupled.scala 275:95]
  reg [2:0] ram_size [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_burst [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_burst_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_burst_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_burst_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_burst_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_burst_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_burst_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_burst_MPORT_en; // @[Decoupled.scala 275:95]
  reg [3:0] ram_echo_tl_state_size [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [3:0] ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_size_MPORT_en; // @[Decoupled.scala 275:95]
  reg [1:0] ram_echo_tl_state_source [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire [1:0] ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_echo_tl_state_source_MPORT_en; // @[Decoupled.scala 275:95]
  reg  ram_wen [0:0]; // @[Decoupled.scala 275:95]
  wire  ram_wen_io_deq_bits_MPORT_en; // @[Decoupled.scala 275:95]
  wire  ram_wen_io_deq_bits_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_wen_io_deq_bits_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_wen_MPORT_data; // @[Decoupled.scala 275:95]
  wire  ram_wen_MPORT_addr; // @[Decoupled.scala 275:95]
  wire  ram_wen_MPORT_mask; // @[Decoupled.scala 275:95]
  wire  ram_wen_MPORT_en; // @[Decoupled.scala 275:95]
  reg  maybe_full; // @[Decoupled.scala 278:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 280:28]
  wire  _do_enq_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 52:35]
  wire  _do_deq_T = io_deq_ready & io_deq_valid; // @[Decoupled.scala 52:35]
  wire  _GEN_20 = io_deq_ready ? 1'h0 : _do_enq_T; // @[Decoupled.scala 320:{26,35}]
  wire  do_enq = empty ? _GEN_20 : _do_enq_T; // @[Decoupled.scala 317:17]
  wire  do_deq = empty ? 1'h0 : _do_deq_T; // @[Decoupled.scala 317:17 319:14]
  assign ram_id_io_deq_bits_MPORT_en = 1'h1;
  assign ram_id_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_id_io_deq_bits_MPORT_data = ram_id[ram_id_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_id_MPORT_data = 1'h0;
  assign ram_id_MPORT_addr = 1'h0;
  assign ram_id_MPORT_mask = 1'h1;
  assign ram_id_MPORT_en = empty ? _GEN_20 : _do_enq_T;
  assign ram_addr_io_deq_bits_MPORT_en = 1'h1;
  assign ram_addr_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_addr_io_deq_bits_MPORT_data = ram_addr[ram_addr_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_addr_MPORT_data = io_enq_bits_addr;
  assign ram_addr_MPORT_addr = 1'h0;
  assign ram_addr_MPORT_mask = 1'h1;
  assign ram_addr_MPORT_en = empty ? _GEN_20 : _do_enq_T;
  assign ram_len_io_deq_bits_MPORT_en = 1'h1;
  assign ram_len_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_len_io_deq_bits_MPORT_data = ram_len[ram_len_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_len_MPORT_data = io_enq_bits_len;
  assign ram_len_MPORT_addr = 1'h0;
  assign ram_len_MPORT_mask = 1'h1;
  assign ram_len_MPORT_en = empty ? _GEN_20 : _do_enq_T;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = 1'h0;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = empty ? _GEN_20 : _do_enq_T;
  assign ram_burst_io_deq_bits_MPORT_en = 1'h1;
  assign ram_burst_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_burst_io_deq_bits_MPORT_data = ram_burst[ram_burst_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_burst_MPORT_data = 2'h1;
  assign ram_burst_MPORT_addr = 1'h0;
  assign ram_burst_MPORT_mask = 1'h1;
  assign ram_burst_MPORT_en = empty ? _GEN_20 : _do_enq_T;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_size_io_deq_bits_MPORT_data =
    ram_echo_tl_state_size[ram_echo_tl_state_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_size_MPORT_data = io_enq_bits_echo_tl_state_size;
  assign ram_echo_tl_state_size_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_size_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_size_MPORT_en = empty ? _GEN_20 : _do_enq_T;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_source_io_deq_bits_MPORT_data =
    ram_echo_tl_state_source[ram_echo_tl_state_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_echo_tl_state_source_MPORT_data = io_enq_bits_echo_tl_state_source;
  assign ram_echo_tl_state_source_MPORT_addr = 1'h0;
  assign ram_echo_tl_state_source_MPORT_mask = 1'h1;
  assign ram_echo_tl_state_source_MPORT_en = empty ? _GEN_20 : _do_enq_T;
  assign ram_wen_io_deq_bits_MPORT_en = 1'h1;
  assign ram_wen_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_wen_io_deq_bits_MPORT_data = ram_wen[ram_wen_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 275:95]
  assign ram_wen_MPORT_data = io_enq_bits_wen;
  assign ram_wen_MPORT_addr = 1'h0;
  assign ram_wen_MPORT_mask = 1'h1;
  assign ram_wen_MPORT_en = empty ? _GEN_20 : _do_enq_T;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 305:19]
  assign io_deq_valid = io_enq_valid | ~empty; // @[Decoupled.scala 304:16 316:{24,39}]
  assign io_deq_bits_id = empty ? 1'h0 : ram_id_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_addr = empty ? io_enq_bits_addr : ram_addr_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_len = empty ? io_enq_bits_len : ram_len_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_size = empty ? io_enq_bits_size : ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_burst = empty ? 2'h1 : ram_burst_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_echo_tl_state_size = empty ? io_enq_bits_echo_tl_state_size :
    ram_echo_tl_state_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_echo_tl_state_source = empty ? io_enq_bits_echo_tl_state_source :
    ram_echo_tl_state_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  assign io_deq_bits_wen = empty ? io_enq_bits_wen : ram_wen_io_deq_bits_MPORT_data; // @[Decoupled.scala 312:17 317:17 318:19]
  always @(posedge clock) begin
    if (ram_id_MPORT_en & ram_id_MPORT_mask) begin
      ram_id[ram_id_MPORT_addr] <= ram_id_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_addr_MPORT_en & ram_addr_MPORT_mask) begin
      ram_addr[ram_addr_MPORT_addr] <= ram_addr_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_len_MPORT_en & ram_len_MPORT_mask) begin
      ram_len[ram_len_MPORT_addr] <= ram_len_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_burst_MPORT_en & ram_burst_MPORT_mask) begin
      ram_burst[ram_burst_MPORT_addr] <= ram_burst_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_size_MPORT_en & ram_echo_tl_state_size_MPORT_mask) begin
      ram_echo_tl_state_size[ram_echo_tl_state_size_MPORT_addr] <= ram_echo_tl_state_size_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_echo_tl_state_source_MPORT_en & ram_echo_tl_state_source_MPORT_mask) begin
      ram_echo_tl_state_source[ram_echo_tl_state_source_MPORT_addr] <= ram_echo_tl_state_source_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (ram_wen_MPORT_en & ram_wen_MPORT_mask) begin
      ram_wen[ram_wen_MPORT_addr] <= ram_wen_MPORT_data; // @[Decoupled.scala 275:95]
    end
    if (reset) begin // @[Decoupled.scala 278:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 278:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 295:27]
      if (empty) begin // @[Decoupled.scala 317:17]
        if (io_deq_ready) begin // @[Decoupled.scala 320:26]
          maybe_full <= 1'h0; // @[Decoupled.scala 320:35]
        end else begin
          maybe_full <= _do_enq_T;
        end
      end else begin
        maybe_full <= _do_enq_T;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_id[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_addr[initvar] = _RAND_1[11:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_len[initvar] = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_size[initvar] = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_burst[initvar] = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_echo_tl_state_size[initvar] = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_echo_tl_state_source[initvar] = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_wen[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  maybe_full = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLToAXI4(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [11:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_aw_ready,
  output        auto_out_aw_valid,
  output        auto_out_aw_bits_id,
  output [11:0] auto_out_aw_bits_addr,
  output [7:0]  auto_out_aw_bits_len,
  output [2:0]  auto_out_aw_bits_size,
  output [1:0]  auto_out_aw_bits_burst,
  output [3:0]  auto_out_aw_bits_echo_tl_state_size,
  output [1:0]  auto_out_aw_bits_echo_tl_state_source,
  input         auto_out_w_ready,
  output        auto_out_w_valid,
  output [31:0] auto_out_w_bits_data,
  output [3:0]  auto_out_w_bits_strb,
  output        auto_out_w_bits_last,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_resp,
  input  [3:0]  auto_out_b_bits_echo_tl_state_size,
  input  [1:0]  auto_out_b_bits_echo_tl_state_source,
  input         auto_out_ar_ready,
  output        auto_out_ar_valid,
  output        auto_out_ar_bits_id,
  output [11:0] auto_out_ar_bits_addr,
  output [7:0]  auto_out_ar_bits_len,
  output [2:0]  auto_out_ar_bits_size,
  output [1:0]  auto_out_ar_bits_burst,
  output [3:0]  auto_out_ar_bits_echo_tl_state_size,
  output [1:0]  auto_out_ar_bits_echo_tl_state_source,
  output        auto_out_r_ready,
  input         auto_out_r_valid,
  input  [31:0] auto_out_r_bits_data,
  input  [1:0]  auto_out_r_bits_resp,
  input  [3:0]  auto_out_r_bits_echo_tl_state_size,
  input  [1:0]  auto_out_r_bits_echo_tl_state_source,
  input         auto_out_r_bits_last
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [11:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  deq_clock; // @[Decoupled.scala 377:21]
  wire  deq_reset; // @[Decoupled.scala 377:21]
  wire  deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [31:0] deq_io_enq_bits_data; // @[Decoupled.scala 377:21]
  wire [3:0] deq_io_enq_bits_strb; // @[Decoupled.scala 377:21]
  wire  deq_io_enq_bits_last; // @[Decoupled.scala 377:21]
  wire  deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire [31:0] deq_io_deq_bits_data; // @[Decoupled.scala 377:21]
  wire [3:0] deq_io_deq_bits_strb; // @[Decoupled.scala 377:21]
  wire  deq_io_deq_bits_last; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_clock; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_reset; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_io_enq_ready; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_io_enq_valid; // @[Decoupled.scala 377:21]
  wire [11:0] queue_arw_deq_io_enq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] queue_arw_deq_io_enq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] queue_arw_deq_io_enq_bits_size; // @[Decoupled.scala 377:21]
  wire [3:0] queue_arw_deq_io_enq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] queue_arw_deq_io_enq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_io_enq_bits_wen; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_io_deq_ready; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_io_deq_valid; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_io_deq_bits_id; // @[Decoupled.scala 377:21]
  wire [11:0] queue_arw_deq_io_deq_bits_addr; // @[Decoupled.scala 377:21]
  wire [7:0] queue_arw_deq_io_deq_bits_len; // @[Decoupled.scala 377:21]
  wire [2:0] queue_arw_deq_io_deq_bits_size; // @[Decoupled.scala 377:21]
  wire [1:0] queue_arw_deq_io_deq_bits_burst; // @[Decoupled.scala 377:21]
  wire [3:0] queue_arw_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 377:21]
  wire [1:0] queue_arw_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 377:21]
  wire  queue_arw_deq_io_deq_bits_wen; // @[Decoupled.scala 377:21]
  wire  a_isPut = ~auto_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [2:0] count_1; // @[ToAXI4.scala 254:28]
  wire  idle = count_1 == 3'h0; // @[ToAXI4.scala 256:26]
  reg  write; // @[ToAXI4.scala 255:24]
  wire  mismatch = write != a_isPut; // @[ToAXI4.scala 267:50]
  wire  idStall_0 = ~idle & mismatch | count_1 == 3'h4; // @[ToAXI4.scala 268:34]
  reg [7:0] counter; // @[Edges.scala 228:27]
  wire  a_first = counter == 8'h0; // @[Edges.scala 230:25]
  wire  stall = idStall_0 & a_first; // @[ToAXI4.scala 195:49]
  wire  _bundleIn_0_a_ready_T = ~stall; // @[ToAXI4.scala 196:21]
  reg  doneAW; // @[ToAXI4.scala 161:30]
  wire  out_arw_ready = queue_arw_deq_io_enq_ready; // @[ToAXI4.scala 147:25 Decoupled.scala 381:17]
  wire  _bundleIn_0_a_ready_T_1 = doneAW | out_arw_ready; // @[ToAXI4.scala 196:52]
  wire  out_w_ready = deq_io_enq_ready; // @[ToAXI4.scala 148:23 Decoupled.scala 381:17]
  wire  _bundleIn_0_a_ready_T_3 = a_isPut ? (doneAW | out_arw_ready) & out_w_ready : out_arw_ready; // @[ToAXI4.scala 196:34]
  wire  bundleIn_0_a_ready = ~stall & _bundleIn_0_a_ready_T_3; // @[ToAXI4.scala 196:28]
  wire  _T = bundleIn_0_a_ready & auto_in_a_valid; // @[Decoupled.scala 52:35]
  wire [24:0] _beats1_decode_T_1 = 25'h3ff << auto_in_a_bits_size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode = _beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire [7:0] beats1 = a_isPut ? beats1_decode : 8'h0; // @[Edges.scala 220:14]
  wire [7:0] counter1 = counter - 8'h1; // @[Edges.scala 229:28]
  wire  a_last = counter == 8'h1 | beats1 == 8'h0; // @[Edges.scala 231:37]
  wire  queue_arw_bits_wen = queue_arw_deq_io_deq_bits_wen; // @[Decoupled.scala 417:19 418:14]
  wire  queue_arw_valid = queue_arw_deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  wire [3:0] _out_arw_bits_size_T_1 = auto_in_a_bits_size >= 4'h2 ? 4'h2 : auto_in_a_bits_size; // @[ToAXI4.scala 169:23]
  wire  _out_arw_valid_T_1 = _bundleIn_0_a_ready_T & auto_in_a_valid; // @[ToAXI4.scala 197:31]
  wire  _out_arw_valid_T_4 = a_isPut ? ~doneAW & out_w_ready : 1'h1; // @[ToAXI4.scala 197:51]
  wire  out_arw_valid = _bundleIn_0_a_ready_T & auto_in_a_valid & _out_arw_valid_T_4; // @[ToAXI4.scala 197:45]
  reg  r_holds_d; // @[ToAXI4.scala 206:30]
  reg [2:0] b_delay; // @[ToAXI4.scala 209:24]
  wire  r_wins = auto_out_r_valid & b_delay != 3'h7 | r_holds_d; // @[ToAXI4.scala 215:57]
  wire  bundleOut_0_r_ready = auto_in_d_ready & r_wins; // @[ToAXI4.scala 217:33]
  wire  _T_2 = bundleOut_0_r_ready & auto_out_r_valid; // @[Decoupled.scala 52:35]
  wire  bundleOut_0_b_ready = auto_in_d_ready & ~r_wins; // @[ToAXI4.scala 218:33]
  wire [2:0] _b_delay_T_1 = b_delay + 3'h1; // @[ToAXI4.scala 211:28]
  wire  bundleIn_0_d_valid = r_wins ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala 219:24]
  reg  r_first; // @[ToAXI4.scala 224:28]
  wire  _GEN_12 = _T_2 ? auto_out_r_bits_last : r_first; // @[ToAXI4.scala 225:27 224:28 225:37]
  wire  _r_denied_T = auto_out_r_bits_resp == 2'h3; // @[ToAXI4.scala 226:39]
  reg  r_denied_r; // @[Reg.scala 19:16]
  wire  _GEN_13 = r_first ? _r_denied_T : r_denied_r; // @[Reg.scala 19:16 20:{18,22}]
  wire  r_corrupt = auto_out_r_bits_resp != 2'h0; // @[ToAXI4.scala 227:39]
  wire  b_denied = auto_out_b_bits_resp != 2'h0; // @[ToAXI4.scala 228:39]
  wire  r_d_corrupt = r_corrupt | _GEN_13; // @[ToAXI4.scala 230:100]
  wire  d_last = r_wins ? auto_out_r_bits_last : 1'h1; // @[ToAXI4.scala 244:23]
  wire  inc = out_arw_ready & out_arw_valid; // @[Decoupled.scala 52:35]
  wire  _dec_T_1 = auto_in_d_ready & bundleIn_0_d_valid; // @[Decoupled.scala 52:35]
  wire  dec = d_last & _dec_T_1; // @[ToAXI4.scala 259:32]
  wire [2:0] _GEN_15 = {{2'd0}, inc}; // @[ToAXI4.scala 260:24]
  wire [2:0] _count_T_2 = count_1 + _GEN_15; // @[ToAXI4.scala 260:24]
  wire [2:0] _GEN_16 = {{2'd0}, dec}; // @[ToAXI4.scala 260:37]
  wire [2:0] _count_T_4 = _count_T_2 - _GEN_16; // @[ToAXI4.scala 260:37]
  wire  _T_10 = ~reset; // @[ToAXI4.scala 262:16]
  TLMonitor monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Queue_2 deq ( // @[Decoupled.scala 377:21]
    .clock(deq_clock),
    .reset(deq_reset),
    .io_enq_ready(deq_io_enq_ready),
    .io_enq_valid(deq_io_enq_valid),
    .io_enq_bits_data(deq_io_enq_bits_data),
    .io_enq_bits_strb(deq_io_enq_bits_strb),
    .io_enq_bits_last(deq_io_enq_bits_last),
    .io_deq_ready(deq_io_deq_ready),
    .io_deq_valid(deq_io_deq_valid),
    .io_deq_bits_data(deq_io_deq_bits_data),
    .io_deq_bits_strb(deq_io_deq_bits_strb),
    .io_deq_bits_last(deq_io_deq_bits_last)
  );
  Queue_15 queue_arw_deq ( // @[Decoupled.scala 377:21]
    .clock(queue_arw_deq_clock),
    .reset(queue_arw_deq_reset),
    .io_enq_ready(queue_arw_deq_io_enq_ready),
    .io_enq_valid(queue_arw_deq_io_enq_valid),
    .io_enq_bits_addr(queue_arw_deq_io_enq_bits_addr),
    .io_enq_bits_len(queue_arw_deq_io_enq_bits_len),
    .io_enq_bits_size(queue_arw_deq_io_enq_bits_size),
    .io_enq_bits_echo_tl_state_size(queue_arw_deq_io_enq_bits_echo_tl_state_size),
    .io_enq_bits_echo_tl_state_source(queue_arw_deq_io_enq_bits_echo_tl_state_source),
    .io_enq_bits_wen(queue_arw_deq_io_enq_bits_wen),
    .io_deq_ready(queue_arw_deq_io_deq_ready),
    .io_deq_valid(queue_arw_deq_io_deq_valid),
    .io_deq_bits_id(queue_arw_deq_io_deq_bits_id),
    .io_deq_bits_addr(queue_arw_deq_io_deq_bits_addr),
    .io_deq_bits_len(queue_arw_deq_io_deq_bits_len),
    .io_deq_bits_size(queue_arw_deq_io_deq_bits_size),
    .io_deq_bits_burst(queue_arw_deq_io_deq_bits_burst),
    .io_deq_bits_echo_tl_state_size(queue_arw_deq_io_deq_bits_echo_tl_state_size),
    .io_deq_bits_echo_tl_state_source(queue_arw_deq_io_deq_bits_echo_tl_state_source),
    .io_deq_bits_wen(queue_arw_deq_io_deq_bits_wen)
  );
  assign auto_in_a_ready = ~stall & _bundleIn_0_a_ready_T_3; // @[ToAXI4.scala 196:28]
  assign auto_in_d_valid = r_wins ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala 219:24]
  assign auto_in_d_bits_opcode = r_wins ? 3'h1 : 3'h0; // @[ToAXI4.scala 237:23]
  assign auto_in_d_bits_size = r_wins ? auto_out_r_bits_echo_tl_state_size : auto_out_b_bits_echo_tl_state_size; // @[ToAXI4.scala 237:23]
  assign auto_in_d_bits_source = r_wins ? auto_out_r_bits_echo_tl_state_source : auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala 237:23]
  assign auto_in_d_bits_denied = r_wins ? _GEN_13 : b_denied; // @[ToAXI4.scala 237:23]
  assign auto_in_d_bits_data = auto_out_r_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = r_wins & r_d_corrupt; // @[ToAXI4.scala 237:23]
  assign auto_out_aw_valid = queue_arw_valid & queue_arw_bits_wen; // @[ToAXI4.scala 156:39]
  assign auto_out_aw_bits_id = queue_arw_deq_io_deq_bits_id; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_addr = queue_arw_deq_io_deq_bits_addr; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_len = queue_arw_deq_io_deq_bits_len; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_size = queue_arw_deq_io_deq_bits_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_burst = queue_arw_deq_io_deq_bits_burst; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_echo_tl_state_size = queue_arw_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_aw_bits_echo_tl_state_source = queue_arw_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_w_valid = deq_io_deq_valid; // @[Decoupled.scala 417:19 419:15]
  assign auto_out_w_bits_data = deq_io_deq_bits_data; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_w_bits_strb = deq_io_deq_bits_strb; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_w_bits_last = deq_io_deq_bits_last; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_b_ready = auto_in_d_ready & ~r_wins; // @[ToAXI4.scala 218:33]
  assign auto_out_ar_valid = queue_arw_valid & ~queue_arw_bits_wen; // @[ToAXI4.scala 155:39]
  assign auto_out_ar_bits_id = queue_arw_deq_io_deq_bits_id; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_addr = queue_arw_deq_io_deq_bits_addr; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_len = queue_arw_deq_io_deq_bits_len; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_size = queue_arw_deq_io_deq_bits_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_burst = queue_arw_deq_io_deq_bits_burst; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_echo_tl_state_size = queue_arw_deq_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_ar_bits_echo_tl_state_source = queue_arw_deq_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala 417:19 418:14]
  assign auto_out_r_ready = auto_in_d_ready & r_wins; // @[ToAXI4.scala 217:33]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = ~stall & _bundleIn_0_a_ready_T_3; // @[ToAXI4.scala 196:28]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = r_wins ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala 219:24]
  assign monitor_io_in_d_bits_opcode = r_wins ? 3'h1 : 3'h0; // @[ToAXI4.scala 237:23]
  assign monitor_io_in_d_bits_size = r_wins ? auto_out_r_bits_echo_tl_state_size : auto_out_b_bits_echo_tl_state_size; // @[ToAXI4.scala 237:23]
  assign monitor_io_in_d_bits_source = r_wins ? auto_out_r_bits_echo_tl_state_source :
    auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala 237:23]
  assign monitor_io_in_d_bits_denied = r_wins ? _GEN_13 : b_denied; // @[ToAXI4.scala 237:23]
  assign monitor_io_in_d_bits_corrupt = r_wins & r_d_corrupt; // @[ToAXI4.scala 237:23]
  assign deq_clock = clock;
  assign deq_reset = reset;
  assign deq_io_enq_valid = _out_arw_valid_T_1 & a_isPut & _bundleIn_0_a_ready_T_1; // @[ToAXI4.scala 199:54]
  assign deq_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_strb = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign deq_io_enq_bits_last = counter == 8'h1 | beats1 == 8'h0; // @[Edges.scala 231:37]
  assign deq_io_deq_ready = auto_out_w_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign queue_arw_deq_clock = clock;
  assign queue_arw_deq_reset = reset;
  assign queue_arw_deq_io_enq_valid = _bundleIn_0_a_ready_T & auto_in_a_valid & _out_arw_valid_T_4; // @[ToAXI4.scala 197:45]
  assign queue_arw_deq_io_enq_bits_addr = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign queue_arw_deq_io_enq_bits_len = _beats1_decode_T_3[9:2]; // @[ToAXI4.scala 168:84]
  assign queue_arw_deq_io_enq_bits_size = _out_arw_bits_size_T_1[2:0]; // @[ToAXI4.scala 147:25 169:17]
  assign queue_arw_deq_io_enq_bits_echo_tl_state_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign queue_arw_deq_io_enq_bits_echo_tl_state_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign queue_arw_deq_io_enq_bits_wen = ~auto_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  assign queue_arw_deq_io_deq_ready = queue_arw_bits_wen ? auto_out_aw_ready : auto_out_ar_ready; // @[ToAXI4.scala 157:29]
  always @(posedge clock) begin
    if (reset) begin // @[ToAXI4.scala 254:28]
      count_1 <= 3'h0; // @[ToAXI4.scala 254:28]
    end else begin
      count_1 <= _count_T_4; // @[ToAXI4.scala 260:15]
    end
    if (inc) begin // @[ToAXI4.scala 265:20]
      write <= a_isPut; // @[ToAXI4.scala 265:28]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_isPut) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 8'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    if (reset) begin // @[ToAXI4.scala 161:30]
      doneAW <= 1'h0; // @[ToAXI4.scala 161:30]
    end else if (_T) begin // @[ToAXI4.scala 162:26]
      doneAW <= ~a_last; // @[ToAXI4.scala 162:35]
    end
    if (reset) begin // @[ToAXI4.scala 206:30]
      r_holds_d <= 1'h0; // @[ToAXI4.scala 206:30]
    end else if (_T_2) begin // @[ToAXI4.scala 207:27]
      r_holds_d <= ~auto_out_r_bits_last; // @[ToAXI4.scala 207:39]
    end
    if (auto_out_b_valid & ~bundleOut_0_b_ready) begin // @[ToAXI4.scala 210:42]
      b_delay <= _b_delay_T_1; // @[ToAXI4.scala 211:17]
    end else begin
      b_delay <= 3'h0; // @[ToAXI4.scala 213:17]
    end
    r_first <= reset | _GEN_12; // @[ToAXI4.scala 224:{28,28}]
    if (r_first) begin // @[Reg.scala 20:18]
      r_denied_r <= _r_denied_T; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~dec | count_1 != 3'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ToAXI4.scala:262 assert (!dec || count =/= UInt(0))        // underflow\n"); // @[ToAXI4.scala 262:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~dec | count_1 != 3'h0) & ~reset) begin
          $fatal; // @[ToAXI4.scala 262:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_10 & ~(~inc | count_1 != 3'h4)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ToAXI4.scala:263 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 263:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~inc | count_1 != 3'h4) & _T_10) begin
          $fatal; // @[ToAXI4.scala 263:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  count_1 = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  write = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  counter = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  doneAW = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  r_holds_d = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  b_delay = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  r_first = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  r_denied_r = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFilter(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [10:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [11:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = {{1'd0}, auto_in_a_bits_address}; // @[Nodes.scala 1207:84 Filter.scala 58:11]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_1(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [10:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [24:0] _is_aligned_mask_T_1 = 25'h3ff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [9:0] is_aligned_mask = ~_is_aligned_mask_T_1[9:0]; // @[package.scala 234:46]
  wire [10:0] _GEN_62 = {{1'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [10:0] _is_aligned_T = io_in_a_bits_address & _GEN_62; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 11'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 33:92]
  wire [11:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_22 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire [11:0] _T_36 = $signed(_T_12) & 12'sh800; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 12'sh0; // @[Parameters.scala 137:67]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 4'ha; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _T_22 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_413 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_417 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_469 = _T_417 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire [7:0] a_first_beats1_decode = is_aligned_mask[9:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [7:0] a_first_counter; // @[Edges.scala 228:27]
  wire [7:0] a_first_counter1 = a_first_counter - 8'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 8'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [10:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire [24:0] _d_first_beats1_decode_T_1 = 25'h3ff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [9:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [7:0] d_first_counter; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1 = d_first_counter - 8'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 8'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_588 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [3:0] inflight; // @[Monitor.scala 611:27]
  reg [15:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [31:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [7:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [7:0] a_first_counter1_1 = a_first_counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala 230:25]
  reg [7:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1_1 = d_first_counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_64 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_64}; // @[Monitor.scala 634:69]
  wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [31:0] _GEN_71 = {{16'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [31:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_71; // @[Monitor.scala 638:91]
  wire [31:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_597 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_73 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_73}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_328 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_328 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_329 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_329 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [3:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [3:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_330 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_330 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_331 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_331 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [46:0] _GEN_23 = _T_608 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _T_608 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [3:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_75 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [3:0] _inflight_T_1 = ~d_clr_wo_ready; // @[Monitor.scala 702:38]
  wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [15:0] a_opcodes_set = _GEN_19[15:0];
  wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [15:0] d_opcodes_clr = _GEN_23[15:0];
  wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [31:0] a_sizes_set = _GEN_20[31:0];
  wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [31:0] d_sizes_clr = _GEN_24[31:0];
  wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_1; // @[Monitor.scala 723:35]
  reg [31:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [7:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1_2 = d_first_counter_2 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala 230:25]
  wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [31:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_71; // @[Monitor.scala 747:93]
  wire [31:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala 747:146]
  wire  _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [3:0] d_clr_wo_ready_1 = io_in_d_valid & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 779:89 780:22]
  wire [46:0] _GEN_69 = _T_696 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [3:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_714 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] _inflight_T_4 = ~d_clr_wo_ready_1; // @[Monitor.scala 809:46]
  wire [3:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [31:0] d_sizes_clr_1 = _GEN_69[31:0];
  wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [31:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 8'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 8'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 4'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 16'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 32'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 8'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 8'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | io_in_d_valid) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 4'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 32'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 8'h0; // @[Edges.scala 228:27]
    end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 8'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (io_in_d_valid) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_22) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_22 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_469 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_T_469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_469 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_588 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~io_in_a_ready) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~io_in_a_ready & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_704[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_704[0] & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_714) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_714 & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_739) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_739 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  size = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  source = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  address = _RAND_4[10:0];
  _RAND_5 = {1{`RANDOM}};
  d_first_counter = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  opcode_1 = _RAND_6[2:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[3:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  denied = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[3:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[15:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[7:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[7:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Atomics(
  input  [2:0]  io_a_opcode,
  input  [3:0]  io_a_mask,
  input  [31:0] io_a_data,
  input  [31:0] io_data_in,
  output [31:0] io_data_out
);
  wire [3:0] _signBit_T = ~io_a_mask; // @[Atomics.scala 23:42]
  wire [3:0] _signBit_T_2 = {1'h1,_signBit_T[3:1]}; // @[Cat.scala 33:92]
  wire [3:0] signBit = io_a_mask & _signBit_T_2; // @[Atomics.scala 23:27]
  wire [31:0] inv_d = ~io_data_in; // @[Atomics.scala 24:38]
  wire [7:0] _sum_T_5 = io_a_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_7 = io_a_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_9 = io_a_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_11 = io_a_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [31:0] _sum_T_12 = {_sum_T_11,_sum_T_9,_sum_T_7,_sum_T_5}; // @[Cat.scala 33:92]
  wire [31:0] _sum_T_13 = _sum_T_12 & io_a_data; // @[Atomics.scala 25:44]
  wire [31:0] sum = _sum_T_13 + inv_d; // @[Atomics.scala 25:57]
  wire [3:0] _sign_a_T_32 = {io_a_data[31],io_a_data[23],io_a_data[15],io_a_data[7]}; // @[Cat.scala 33:92]
  wire [3:0] _sign_a_T_33 = _sign_a_T_32 & signBit; // @[Atomics.scala 26:83]
  wire  sign_a = |_sign_a_T_33; // @[Atomics.scala 26:97]
  wire [3:0] _sign_d_T_32 = {io_data_in[31],io_data_in[23],io_data_in[15],io_data_in[7]}; // @[Cat.scala 33:92]
  wire [3:0] _sign_d_T_33 = _sign_d_T_32 & signBit; // @[Atomics.scala 26:83]
  wire  sign_d = |_sign_d_T_33; // @[Atomics.scala 26:97]
  wire [3:0] _sign_s_T_32 = {sum[31],sum[23],sum[15],sum[7]}; // @[Cat.scala 33:92]
  wire [3:0] _sign_s_T_33 = _sign_s_T_32 & signBit; // @[Atomics.scala 26:83]
  wire  sign_s = |_sign_s_T_33; // @[Atomics.scala 26:97]
  wire  a_bigger_uneq = ~sign_a; // @[Atomics.scala 30:32]
  wire  a_bigger = sign_a == sign_d ? ~sign_s : a_bigger_uneq; // @[Atomics.scala 31:21]
  wire  pick_a = ~a_bigger; // @[Atomics.scala 32:25]
  wire [1:0] _logical_T_64 = {io_a_data[0],io_data_in[0]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_65 = 4'h6 >> _logical_T_64; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_67 = {io_a_data[1],io_data_in[1]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_68 = 4'h6 >> _logical_T_67; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_70 = {io_a_data[2],io_data_in[2]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_71 = 4'h6 >> _logical_T_70; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_73 = {io_a_data[3],io_data_in[3]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_74 = 4'h6 >> _logical_T_73; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_76 = {io_a_data[4],io_data_in[4]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_77 = 4'h6 >> _logical_T_76; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_79 = {io_a_data[5],io_data_in[5]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_80 = 4'h6 >> _logical_T_79; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_82 = {io_a_data[6],io_data_in[6]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_83 = 4'h6 >> _logical_T_82; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_85 = {io_a_data[7],io_data_in[7]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_86 = 4'h6 >> _logical_T_85; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_88 = {io_a_data[8],io_data_in[8]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_89 = 4'h6 >> _logical_T_88; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_91 = {io_a_data[9],io_data_in[9]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_92 = 4'h6 >> _logical_T_91; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_94 = {io_a_data[10],io_data_in[10]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_95 = 4'h6 >> _logical_T_94; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_97 = {io_a_data[11],io_data_in[11]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_98 = 4'h6 >> _logical_T_97; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_100 = {io_a_data[12],io_data_in[12]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_101 = 4'h6 >> _logical_T_100; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_103 = {io_a_data[13],io_data_in[13]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_104 = 4'h6 >> _logical_T_103; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_106 = {io_a_data[14],io_data_in[14]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_107 = 4'h6 >> _logical_T_106; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_109 = {io_a_data[15],io_data_in[15]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_110 = 4'h6 >> _logical_T_109; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_112 = {io_a_data[16],io_data_in[16]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_113 = 4'h6 >> _logical_T_112; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_115 = {io_a_data[17],io_data_in[17]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_116 = 4'h6 >> _logical_T_115; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_118 = {io_a_data[18],io_data_in[18]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_119 = 4'h6 >> _logical_T_118; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_121 = {io_a_data[19],io_data_in[19]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_122 = 4'h6 >> _logical_T_121; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_124 = {io_a_data[20],io_data_in[20]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_125 = 4'h6 >> _logical_T_124; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_127 = {io_a_data[21],io_data_in[21]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_128 = 4'h6 >> _logical_T_127; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_130 = {io_a_data[22],io_data_in[22]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_131 = 4'h6 >> _logical_T_130; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_133 = {io_a_data[23],io_data_in[23]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_134 = 4'h6 >> _logical_T_133; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_136 = {io_a_data[24],io_data_in[24]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_137 = 4'h6 >> _logical_T_136; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_139 = {io_a_data[25],io_data_in[25]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_140 = 4'h6 >> _logical_T_139; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_142 = {io_a_data[26],io_data_in[26]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_143 = 4'h6 >> _logical_T_142; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_145 = {io_a_data[27],io_data_in[27]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_146 = 4'h6 >> _logical_T_145; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_148 = {io_a_data[28],io_data_in[28]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_149 = 4'h6 >> _logical_T_148; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_151 = {io_a_data[29],io_data_in[29]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_152 = 4'h6 >> _logical_T_151; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_154 = {io_a_data[30],io_data_in[30]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_155 = 4'h6 >> _logical_T_154; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_157 = {io_a_data[31],io_data_in[31]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_158 = 4'h6 >> _logical_T_157; // @[Atomics.scala 42:8]
  wire [7:0] logical_lo_lo = {_logical_T_86[0],_logical_T_83[0],_logical_T_80[0],_logical_T_77[0],_logical_T_74[0],
    _logical_T_71[0],_logical_T_68[0],_logical_T_65[0]}; // @[Cat.scala 33:92]
  wire [15:0] logical_lo = {_logical_T_110[0],_logical_T_107[0],_logical_T_104[0],_logical_T_101[0],_logical_T_98[0],
    _logical_T_95[0],_logical_T_92[0],_logical_T_89[0],logical_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] logical_hi_lo = {_logical_T_134[0],_logical_T_131[0],_logical_T_128[0],_logical_T_125[0],_logical_T_122[0],
    _logical_T_119[0],_logical_T_116[0],_logical_T_113[0]}; // @[Cat.scala 33:92]
  wire [31:0] logical = {_logical_T_158[0],_logical_T_155[0],_logical_T_152[0],_logical_T_149[0],_logical_T_146[0],
    _logical_T_143[0],_logical_T_140[0],_logical_T_137[0],logical_hi_lo,logical_lo}; // @[Cat.scala 33:92]
  wire [1:0] _select_T_1 = {{1'd0}, pick_a}; // @[Atomics.scala 49:8]
  wire [1:0] _GEN_6 = 3'h2 == io_a_opcode ? _select_T_1 : 2'h1; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_7 = 3'h3 == io_a_opcode ? 2'h3 : _GEN_6; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_8 = 3'h4 == io_a_opcode ? 2'h0 : _GEN_7; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_9 = 3'h5 == io_a_opcode ? 2'h0 : _GEN_8; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_10 = 3'h6 == io_a_opcode ? 2'h0 : _GEN_9; // @[Atomics.scala 46:{19,19}]
  wire [1:0] select = 3'h7 == io_a_opcode ? 2'h0 : _GEN_10; // @[Atomics.scala 46:{19,19}]
  wire [1:0] selects_0 = io_a_mask[0] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_1 = io_a_mask[1] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_2 = io_a_mask[2] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_3 = io_a_mask[3] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [7:0] _GEN_13 = 2'h1 == selects_1 ? io_a_data[15:8] : io_data_in[15:8]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_14 = 2'h2 == selects_1 ? sum[15:8] : _GEN_13; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_15 = 2'h3 == selects_1 ? logical[15:8] : _GEN_14; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_17 = 2'h1 == selects_0 ? io_a_data[7:0] : io_data_in[7:0]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_18 = 2'h2 == selects_0 ? sum[7:0] : _GEN_17; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_19 = 2'h3 == selects_0 ? logical[7:0] : _GEN_18; // @[Cat.scala 33:{92,92}]
  wire [15:0] io_data_out_lo = {_GEN_15,_GEN_19}; // @[Cat.scala 33:92]
  wire [7:0] _GEN_21 = 2'h1 == selects_3 ? io_a_data[31:24] : io_data_in[31:24]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_22 = 2'h2 == selects_3 ? sum[31:24] : _GEN_21; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_23 = 2'h3 == selects_3 ? logical[31:24] : _GEN_22; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_25 = 2'h1 == selects_2 ? io_a_data[23:16] : io_data_in[23:16]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_26 = 2'h2 == selects_2 ? sum[23:16] : _GEN_25; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_27 = 2'h3 == selects_2 ? logical[23:16] : _GEN_26; // @[Cat.scala 33:{92,92}]
  wire [15:0] io_data_out_hi = {_GEN_23,_GEN_27}; // @[Cat.scala 33:92]
  assign io_data_out = {io_data_out_hi,io_data_out_lo}; // @[Cat.scala 33:92]
endmodule
module TLRAMModel(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [10:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [10:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [10:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  reg  shadow_0_valid [0:511]; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_a_shadow_0_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_0_valid_a_shadow_0_addr; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_a_shadow_0_data; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_d_shadow_0_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_0_valid_d_shadow_0_addr; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_d_shadow_0_data; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_MPORT_2_data; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_0_valid_MPORT_2_addr; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_MPORT_2_mask; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_MPORT_2_en; // @[RAMModel.scala 69:45]
  reg [7:0] shadow_0_value [0:511]; // @[RAMModel.scala 69:45]
  wire  shadow_0_value_a_shadow_0_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_0_value_a_shadow_0_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_0_value_a_shadow_0_data; // @[RAMModel.scala 69:45]
  wire  shadow_0_value_d_shadow_0_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_0_value_d_shadow_0_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_0_value_d_shadow_0_data; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_0_value_MPORT_2_data; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_0_value_MPORT_2_addr; // @[RAMModel.scala 69:45]
  wire  shadow_0_value_MPORT_2_mask; // @[RAMModel.scala 69:45]
  wire  shadow_0_value_MPORT_2_en; // @[RAMModel.scala 69:45]
  reg  shadow_1_valid [0:511]; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_a_shadow_1_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_1_valid_a_shadow_1_addr; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_a_shadow_1_data; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_d_shadow_1_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_1_valid_d_shadow_1_addr; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_d_shadow_1_data; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_MPORT_3_data; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_1_valid_MPORT_3_addr; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_MPORT_3_mask; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_MPORT_3_en; // @[RAMModel.scala 69:45]
  reg [7:0] shadow_1_value [0:511]; // @[RAMModel.scala 69:45]
  wire  shadow_1_value_a_shadow_1_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_1_value_a_shadow_1_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_1_value_a_shadow_1_data; // @[RAMModel.scala 69:45]
  wire  shadow_1_value_d_shadow_1_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_1_value_d_shadow_1_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_1_value_d_shadow_1_data; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_1_value_MPORT_3_data; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_1_value_MPORT_3_addr; // @[RAMModel.scala 69:45]
  wire  shadow_1_value_MPORT_3_mask; // @[RAMModel.scala 69:45]
  wire  shadow_1_value_MPORT_3_en; // @[RAMModel.scala 69:45]
  reg  shadow_2_valid [0:511]; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_a_shadow_2_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_2_valid_a_shadow_2_addr; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_a_shadow_2_data; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_d_shadow_2_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_2_valid_d_shadow_2_addr; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_d_shadow_2_data; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_MPORT_4_data; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_2_valid_MPORT_4_addr; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_MPORT_4_mask; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_MPORT_4_en; // @[RAMModel.scala 69:45]
  reg [7:0] shadow_2_value [0:511]; // @[RAMModel.scala 69:45]
  wire  shadow_2_value_a_shadow_2_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_2_value_a_shadow_2_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_2_value_a_shadow_2_data; // @[RAMModel.scala 69:45]
  wire  shadow_2_value_d_shadow_2_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_2_value_d_shadow_2_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_2_value_d_shadow_2_data; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_2_value_MPORT_4_data; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_2_value_MPORT_4_addr; // @[RAMModel.scala 69:45]
  wire  shadow_2_value_MPORT_4_mask; // @[RAMModel.scala 69:45]
  wire  shadow_2_value_MPORT_4_en; // @[RAMModel.scala 69:45]
  reg  shadow_3_valid [0:511]; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_a_shadow_3_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_3_valid_a_shadow_3_addr; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_a_shadow_3_data; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_d_shadow_3_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_3_valid_d_shadow_3_addr; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_d_shadow_3_data; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_MPORT_5_data; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_3_valid_MPORT_5_addr; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_MPORT_5_mask; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_MPORT_5_en; // @[RAMModel.scala 69:45]
  reg [7:0] shadow_3_value [0:511]; // @[RAMModel.scala 69:45]
  wire  shadow_3_value_a_shadow_3_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_3_value_a_shadow_3_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_3_value_a_shadow_3_data; // @[RAMModel.scala 69:45]
  wire  shadow_3_value_d_shadow_3_en; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_3_value_d_shadow_3_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_3_value_d_shadow_3_data; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_3_value_MPORT_5_data; // @[RAMModel.scala 69:45]
  wire [8:0] shadow_3_value_MPORT_5_addr; // @[RAMModel.scala 69:45]
  wire  shadow_3_value_MPORT_5_mask; // @[RAMModel.scala 69:45]
  wire  shadow_3_value_MPORT_5_en; // @[RAMModel.scala 69:45]
  reg [1:0] inc_bytes_0 [0:511]; // @[RAMModel.scala 70:48]
  wire  inc_bytes_0_a_inc_bytes_0_en; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_0_a_inc_bytes_0_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_0_a_inc_bytes_0_data; // @[RAMModel.scala 70:48]
  wire  inc_bytes_0_d_inc_bytes_0_en; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_0_d_inc_bytes_0_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_0_d_inc_bytes_0_data; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_0_MPORT_6_data; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_0_MPORT_6_addr; // @[RAMModel.scala 70:48]
  wire  inc_bytes_0_MPORT_6_mask; // @[RAMModel.scala 70:48]
  wire  inc_bytes_0_MPORT_6_en; // @[RAMModel.scala 70:48]
  reg [1:0] inc_bytes_1 [0:511]; // @[RAMModel.scala 70:48]
  wire  inc_bytes_1_a_inc_bytes_1_en; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_1_a_inc_bytes_1_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_1_a_inc_bytes_1_data; // @[RAMModel.scala 70:48]
  wire  inc_bytes_1_d_inc_bytes_1_en; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_1_d_inc_bytes_1_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_1_d_inc_bytes_1_data; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_1_MPORT_7_data; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_1_MPORT_7_addr; // @[RAMModel.scala 70:48]
  wire  inc_bytes_1_MPORT_7_mask; // @[RAMModel.scala 70:48]
  wire  inc_bytes_1_MPORT_7_en; // @[RAMModel.scala 70:48]
  reg [1:0] inc_bytes_2 [0:511]; // @[RAMModel.scala 70:48]
  wire  inc_bytes_2_a_inc_bytes_2_en; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_2_a_inc_bytes_2_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_2_a_inc_bytes_2_data; // @[RAMModel.scala 70:48]
  wire  inc_bytes_2_d_inc_bytes_2_en; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_2_d_inc_bytes_2_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_2_d_inc_bytes_2_data; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_2_MPORT_8_data; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_2_MPORT_8_addr; // @[RAMModel.scala 70:48]
  wire  inc_bytes_2_MPORT_8_mask; // @[RAMModel.scala 70:48]
  wire  inc_bytes_2_MPORT_8_en; // @[RAMModel.scala 70:48]
  reg [1:0] inc_bytes_3 [0:511]; // @[RAMModel.scala 70:48]
  wire  inc_bytes_3_a_inc_bytes_3_en; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_3_a_inc_bytes_3_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_3_a_inc_bytes_3_data; // @[RAMModel.scala 70:48]
  wire  inc_bytes_3_d_inc_bytes_3_en; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_3_d_inc_bytes_3_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_3_d_inc_bytes_3_data; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_3_MPORT_9_data; // @[RAMModel.scala 70:48]
  wire [8:0] inc_bytes_3_MPORT_9_addr; // @[RAMModel.scala 70:48]
  wire  inc_bytes_3_MPORT_9_mask; // @[RAMModel.scala 70:48]
  wire  inc_bytes_3_MPORT_9_en; // @[RAMModel.scala 70:48]
  reg [1:0] dec_bytes_0 [0:511]; // @[RAMModel.scala 71:48]
  wire  dec_bytes_0_a_dec_bytes_0_en; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_0_a_dec_bytes_0_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_0_a_dec_bytes_0_data; // @[RAMModel.scala 71:48]
  wire  dec_bytes_0_d_dec_bytes_0_en; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_0_d_dec_bytes_0_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_0_d_dec_bytes_0_data; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_0_MPORT_18_data; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_0_MPORT_18_addr; // @[RAMModel.scala 71:48]
  wire  dec_bytes_0_MPORT_18_mask; // @[RAMModel.scala 71:48]
  wire  dec_bytes_0_MPORT_18_en; // @[RAMModel.scala 71:48]
  reg [1:0] dec_bytes_1 [0:511]; // @[RAMModel.scala 71:48]
  wire  dec_bytes_1_a_dec_bytes_1_en; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_1_a_dec_bytes_1_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_1_a_dec_bytes_1_data; // @[RAMModel.scala 71:48]
  wire  dec_bytes_1_d_dec_bytes_1_en; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_1_d_dec_bytes_1_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_1_d_dec_bytes_1_data; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_1_MPORT_19_data; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_1_MPORT_19_addr; // @[RAMModel.scala 71:48]
  wire  dec_bytes_1_MPORT_19_mask; // @[RAMModel.scala 71:48]
  wire  dec_bytes_1_MPORT_19_en; // @[RAMModel.scala 71:48]
  reg [1:0] dec_bytes_2 [0:511]; // @[RAMModel.scala 71:48]
  wire  dec_bytes_2_a_dec_bytes_2_en; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_2_a_dec_bytes_2_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_2_a_dec_bytes_2_data; // @[RAMModel.scala 71:48]
  wire  dec_bytes_2_d_dec_bytes_2_en; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_2_d_dec_bytes_2_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_2_d_dec_bytes_2_data; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_2_MPORT_20_data; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_2_MPORT_20_addr; // @[RAMModel.scala 71:48]
  wire  dec_bytes_2_MPORT_20_mask; // @[RAMModel.scala 71:48]
  wire  dec_bytes_2_MPORT_20_en; // @[RAMModel.scala 71:48]
  reg [1:0] dec_bytes_3 [0:511]; // @[RAMModel.scala 71:48]
  wire  dec_bytes_3_a_dec_bytes_3_en; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_3_a_dec_bytes_3_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_3_a_dec_bytes_3_data; // @[RAMModel.scala 71:48]
  wire  dec_bytes_3_d_dec_bytes_3_en; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_3_d_dec_bytes_3_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_3_d_dec_bytes_3_data; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_3_MPORT_21_data; // @[RAMModel.scala 71:48]
  wire [8:0] dec_bytes_3_MPORT_21_addr; // @[RAMModel.scala 71:48]
  wire  dec_bytes_3_MPORT_21_mask; // @[RAMModel.scala 71:48]
  wire  dec_bytes_3_MPORT_21_en; // @[RAMModel.scala 71:48]
  reg [1:0] inc_trees_0 [0:255]; // @[RAMModel.scala 72:56]
  wire  inc_trees_0_a_inc_trees_0_en; // @[RAMModel.scala 72:56]
  wire [7:0] inc_trees_0_a_inc_trees_0_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_0_a_inc_trees_0_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_0_d_inc_trees_0_en; // @[RAMModel.scala 72:56]
  wire [7:0] inc_trees_0_d_inc_trees_0_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_0_d_inc_trees_0_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_0_MPORT_10_data; // @[RAMModel.scala 72:56]
  wire [7:0] inc_trees_0_MPORT_10_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_0_MPORT_10_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_0_MPORT_10_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_1 [0:127]; // @[RAMModel.scala 72:56]
  wire  inc_trees_1_a_inc_trees_1_en; // @[RAMModel.scala 72:56]
  wire [6:0] inc_trees_1_a_inc_trees_1_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_1_a_inc_trees_1_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_1_d_inc_trees_1_en; // @[RAMModel.scala 72:56]
  wire [6:0] inc_trees_1_d_inc_trees_1_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_1_d_inc_trees_1_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_1_MPORT_11_data; // @[RAMModel.scala 72:56]
  wire [6:0] inc_trees_1_MPORT_11_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_1_MPORT_11_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_1_MPORT_11_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_2 [0:63]; // @[RAMModel.scala 72:56]
  wire  inc_trees_2_a_inc_trees_2_en; // @[RAMModel.scala 72:56]
  wire [5:0] inc_trees_2_a_inc_trees_2_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_2_a_inc_trees_2_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_2_d_inc_trees_2_en; // @[RAMModel.scala 72:56]
  wire [5:0] inc_trees_2_d_inc_trees_2_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_2_d_inc_trees_2_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_2_MPORT_12_data; // @[RAMModel.scala 72:56]
  wire [5:0] inc_trees_2_MPORT_12_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_2_MPORT_12_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_2_MPORT_12_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_3 [0:31]; // @[RAMModel.scala 72:56]
  wire  inc_trees_3_a_inc_trees_3_en; // @[RAMModel.scala 72:56]
  wire [4:0] inc_trees_3_a_inc_trees_3_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_3_a_inc_trees_3_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_3_d_inc_trees_3_en; // @[RAMModel.scala 72:56]
  wire [4:0] inc_trees_3_d_inc_trees_3_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_3_d_inc_trees_3_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_3_MPORT_13_data; // @[RAMModel.scala 72:56]
  wire [4:0] inc_trees_3_MPORT_13_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_3_MPORT_13_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_3_MPORT_13_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_4 [0:15]; // @[RAMModel.scala 72:56]
  wire  inc_trees_4_a_inc_trees_4_en; // @[RAMModel.scala 72:56]
  wire [3:0] inc_trees_4_a_inc_trees_4_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_4_a_inc_trees_4_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_4_d_inc_trees_4_en; // @[RAMModel.scala 72:56]
  wire [3:0] inc_trees_4_d_inc_trees_4_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_4_d_inc_trees_4_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_4_MPORT_14_data; // @[RAMModel.scala 72:56]
  wire [3:0] inc_trees_4_MPORT_14_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_4_MPORT_14_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_4_MPORT_14_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_5 [0:7]; // @[RAMModel.scala 72:56]
  wire  inc_trees_5_a_inc_trees_5_en; // @[RAMModel.scala 72:56]
  wire [2:0] inc_trees_5_a_inc_trees_5_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_5_a_inc_trees_5_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_5_d_inc_trees_5_en; // @[RAMModel.scala 72:56]
  wire [2:0] inc_trees_5_d_inc_trees_5_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_5_d_inc_trees_5_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_5_MPORT_15_data; // @[RAMModel.scala 72:56]
  wire [2:0] inc_trees_5_MPORT_15_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_5_MPORT_15_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_5_MPORT_15_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_6 [0:3]; // @[RAMModel.scala 72:56]
  wire  inc_trees_6_a_inc_trees_6_en; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_a_inc_trees_6_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_a_inc_trees_6_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_6_d_inc_trees_6_en; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_d_inc_trees_6_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_d_inc_trees_6_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_MPORT_16_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_MPORT_16_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_6_MPORT_16_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_6_MPORT_16_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_7 [0:1]; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_a_inc_trees_7_en; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_a_inc_trees_7_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_a_inc_trees_7_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_d_inc_trees_7_en; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_d_inc_trees_7_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_d_inc_trees_7_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_MPORT_17_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_MPORT_17_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_MPORT_17_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_MPORT_17_en; // @[RAMModel.scala 72:56]
  reg [1:0] dec_trees_0 [0:255]; // @[RAMModel.scala 73:56]
  wire  dec_trees_0_a_dec_trees_0_en; // @[RAMModel.scala 73:56]
  wire [7:0] dec_trees_0_a_dec_trees_0_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_0_a_dec_trees_0_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_0_d_dec_trees_0_en; // @[RAMModel.scala 73:56]
  wire [7:0] dec_trees_0_d_dec_trees_0_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_0_d_dec_trees_0_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_0_MPORT_22_data; // @[RAMModel.scala 73:56]
  wire [7:0] dec_trees_0_MPORT_22_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_0_MPORT_22_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_0_MPORT_22_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_1 [0:127]; // @[RAMModel.scala 73:56]
  wire  dec_trees_1_a_dec_trees_1_en; // @[RAMModel.scala 73:56]
  wire [6:0] dec_trees_1_a_dec_trees_1_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_1_a_dec_trees_1_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_1_d_dec_trees_1_en; // @[RAMModel.scala 73:56]
  wire [6:0] dec_trees_1_d_dec_trees_1_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_1_d_dec_trees_1_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_1_MPORT_23_data; // @[RAMModel.scala 73:56]
  wire [6:0] dec_trees_1_MPORT_23_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_1_MPORT_23_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_1_MPORT_23_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_2 [0:63]; // @[RAMModel.scala 73:56]
  wire  dec_trees_2_a_dec_trees_2_en; // @[RAMModel.scala 73:56]
  wire [5:0] dec_trees_2_a_dec_trees_2_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_2_a_dec_trees_2_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_2_d_dec_trees_2_en; // @[RAMModel.scala 73:56]
  wire [5:0] dec_trees_2_d_dec_trees_2_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_2_d_dec_trees_2_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_2_MPORT_24_data; // @[RAMModel.scala 73:56]
  wire [5:0] dec_trees_2_MPORT_24_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_2_MPORT_24_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_2_MPORT_24_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_3 [0:31]; // @[RAMModel.scala 73:56]
  wire  dec_trees_3_a_dec_trees_3_en; // @[RAMModel.scala 73:56]
  wire [4:0] dec_trees_3_a_dec_trees_3_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_3_a_dec_trees_3_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_3_d_dec_trees_3_en; // @[RAMModel.scala 73:56]
  wire [4:0] dec_trees_3_d_dec_trees_3_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_3_d_dec_trees_3_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_3_MPORT_25_data; // @[RAMModel.scala 73:56]
  wire [4:0] dec_trees_3_MPORT_25_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_3_MPORT_25_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_3_MPORT_25_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_4 [0:15]; // @[RAMModel.scala 73:56]
  wire  dec_trees_4_a_dec_trees_4_en; // @[RAMModel.scala 73:56]
  wire [3:0] dec_trees_4_a_dec_trees_4_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_4_a_dec_trees_4_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_4_d_dec_trees_4_en; // @[RAMModel.scala 73:56]
  wire [3:0] dec_trees_4_d_dec_trees_4_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_4_d_dec_trees_4_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_4_MPORT_26_data; // @[RAMModel.scala 73:56]
  wire [3:0] dec_trees_4_MPORT_26_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_4_MPORT_26_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_4_MPORT_26_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_5 [0:7]; // @[RAMModel.scala 73:56]
  wire  dec_trees_5_a_dec_trees_5_en; // @[RAMModel.scala 73:56]
  wire [2:0] dec_trees_5_a_dec_trees_5_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_5_a_dec_trees_5_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_5_d_dec_trees_5_en; // @[RAMModel.scala 73:56]
  wire [2:0] dec_trees_5_d_dec_trees_5_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_5_d_dec_trees_5_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_5_MPORT_27_data; // @[RAMModel.scala 73:56]
  wire [2:0] dec_trees_5_MPORT_27_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_5_MPORT_27_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_5_MPORT_27_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_6 [0:3]; // @[RAMModel.scala 73:56]
  wire  dec_trees_6_a_dec_trees_6_en; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_a_dec_trees_6_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_a_dec_trees_6_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_6_d_dec_trees_6_en; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_d_dec_trees_6_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_d_dec_trees_6_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_MPORT_28_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_MPORT_28_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_6_MPORT_28_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_6_MPORT_28_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_7 [0:1]; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_a_dec_trees_7_en; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_a_dec_trees_7_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_a_dec_trees_7_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_d_dec_trees_7_en; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_d_dec_trees_7_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_d_dec_trees_7_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_MPORT_29_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_MPORT_29_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_MPORT_29_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_MPORT_29_en; // @[RAMModel.scala 73:56]
  wire [2:0] alu_io_a_opcode; // @[RAMModel.scala 157:23]
  wire [3:0] alu_io_a_mask; // @[RAMModel.scala 157:23]
  wire [31:0] alu_io_a_data; // @[RAMModel.scala 157:23]
  wire [31:0] alu_io_data_in; // @[RAMModel.scala 157:23]
  wire [31:0] alu_io_data_out; // @[RAMModel.scala 157:23]
  reg [15:0] crc [0:3]; // @[RAMModel.scala 162:20]
  wire  crc_a_crc_acc_MPORT_en; // @[RAMModel.scala 162:20]
  wire [1:0] crc_a_crc_acc_MPORT_addr; // @[RAMModel.scala 162:20]
  wire [15:0] crc_a_crc_acc_MPORT_data; // @[RAMModel.scala 162:20]
  wire  crc_d_crc_check_MPORT_en; // @[RAMModel.scala 162:20]
  wire [1:0] crc_d_crc_check_MPORT_addr; // @[RAMModel.scala 162:20]
  wire [15:0] crc_d_crc_check_MPORT_data; // @[RAMModel.scala 162:20]
  wire [15:0] crc_MPORT_data; // @[RAMModel.scala 162:20]
  wire [1:0] crc_MPORT_addr; // @[RAMModel.scala 162:20]
  wire  crc_MPORT_mask; // @[RAMModel.scala 162:20]
  wire  crc_MPORT_en; // @[RAMModel.scala 162:20]
  reg  crc_valid [0:3]; // @[RAMModel.scala 163:26]
  wire  crc_valid_a_crc_valid_MPORT_en; // @[RAMModel.scala 163:26]
  wire [1:0] crc_valid_a_crc_valid_MPORT_addr; // @[RAMModel.scala 163:26]
  wire  crc_valid_a_crc_valid_MPORT_data; // @[RAMModel.scala 163:26]
  wire  crc_valid_d_crc_valid_MPORT_en; // @[RAMModel.scala 163:26]
  wire [1:0] crc_valid_d_crc_valid_MPORT_addr; // @[RAMModel.scala 163:26]
  wire  crc_valid_d_crc_valid_MPORT_data; // @[RAMModel.scala 163:26]
  wire  crc_valid_MPORT_1_data; // @[RAMModel.scala 163:26]
  wire [1:0] crc_valid_MPORT_1_addr; // @[RAMModel.scala 163:26]
  wire  crc_valid_MPORT_1_mask; // @[RAMModel.scala 163:26]
  wire  crc_valid_MPORT_1_en; // @[RAMModel.scala 163:26]
  reg [9:0] wipeIndex; // @[RAMModel.scala 46:30]
  wire  wipe = ~wipeIndex[9]; // @[RAMModel.scala 47:18]
  wire [9:0] _GEN_237 = {{9'd0}, wipe}; // @[RAMModel.scala 48:30]
  wire [9:0] _wipeIndex_T_1 = wipeIndex + _GEN_237; // @[RAMModel.scala 48:30]
  wire  _bundleIn_0_a_ready_T = ~wipe; // @[RAMModel.scala 51:36]
  wire  bundleIn_0_a_ready = auto_out_a_ready & ~wipe; // @[RAMModel.scala 51:33]
  wire [3:0] shadow_wen_x9 = wipe ? 4'hf : 4'h0; // @[Bitwise.scala 77:12]
  wire [7:0] inc_trees_wen_x15 = wipe ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  reg [10:0] flight_0_base; // @[RAMModel.scala 82:23]
  reg [3:0] flight_0_size; // @[RAMModel.scala 82:23]
  reg [2:0] flight_0_opcode; // @[RAMModel.scala 82:23]
  reg [10:0] flight_1_base; // @[RAMModel.scala 82:23]
  reg [3:0] flight_1_size; // @[RAMModel.scala 82:23]
  reg [2:0] flight_1_opcode; // @[RAMModel.scala 82:23]
  reg [10:0] flight_2_base; // @[RAMModel.scala 82:23]
  reg [3:0] flight_2_size; // @[RAMModel.scala 82:23]
  reg [2:0] flight_2_opcode; // @[RAMModel.scala 82:23]
  reg [10:0] flight_3_base; // @[RAMModel.scala 82:23]
  reg [3:0] flight_3_size; // @[RAMModel.scala 82:23]
  reg [2:0] flight_3_opcode; // @[RAMModel.scala 82:23]
  wire  _T = bundleIn_0_a_ready & auto_in_a_valid; // @[Decoupled.scala 52:35]
  wire  _d_flight_T_1 = _bundleIn_0_a_ready_T & auto_out_d_valid; // @[Decoupled.scala 52:35]
  wire [24:0] _d_flight_beats1_decode_T_1 = 25'h3ff << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [9:0] _d_flight_beats1_decode_T_3 = ~_d_flight_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] d_flight_beats1_decode = _d_flight_beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire  d_flight_beats1_opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [7:0] d_flight_counter; // @[Edges.scala 228:27]
  wire [7:0] d_flight_counter1 = d_flight_counter - 8'h1; // @[Edges.scala 229:28]
  wire  d_flight_first = d_flight_counter == 8'h0; // @[Edges.scala 230:25]
  reg [10:0] d_flight_base; // @[Reg.scala 19:16]
  reg [3:0] d_flight_size; // @[Reg.scala 19:16]
  reg [2:0] d_flight_opcode; // @[Reg.scala 19:16]
  reg [2:0] a__opcode; // @[RAMModel.scala 96:18]
  reg [3:0] a__size; // @[RAMModel.scala 96:18]
  reg [1:0] a__source; // @[RAMModel.scala 96:18]
  reg [10:0] a__address; // @[RAMModel.scala 96:18]
  reg [3:0] a__mask; // @[RAMModel.scala 96:18]
  reg [31:0] a__data; // @[RAMModel.scala 96:18]
  reg  a_fire; // @[RAMModel.scala 97:23]
  wire [24:0] _beats1_decode_T_1 = 25'h3ff << a__size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode = _beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire  beats1_opdata = ~a__opcode[2]; // @[Edges.scala 91:28]
  wire [7:0] beats1 = beats1_opdata ? beats1_decode : 8'h0; // @[Edges.scala 220:14]
  reg [7:0] counter; // @[Edges.scala 228:27]
  wire [7:0] counter1 = counter - 8'h1; // @[Edges.scala 229:28]
  wire  a_first = counter == 8'h0; // @[Edges.scala 230:25]
  wire [7:0] _count_T = ~counter1; // @[Edges.scala 233:27]
  wire [7:0] count = beats1 & _count_T; // @[Edges.scala 233:25]
  wire [9:0] a_address_inc = {count, 2'h0}; // @[Edges.scala 268:29]
  wire [15:0] a_sizeOH = 16'h1 << a__size; // @[OneHot.scala 57:35]
  wire [10:0] _GEN_238 = {{1'd0}, a_address_inc}; // @[RAMModel.scala 101:33]
  wire [10:0] a_address = a__address | _GEN_238; // @[RAMModel.scala 101:33]
  wire [8:0] a_addr_hi = a_address[10:2]; // @[Edges.scala 191:34]
  wire  a_mask_sizeOH_shiftAmount = a__size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _a_mask_sizeOH_T_1 = 2'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] a_mask_sizeOH = _a_mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _a_mask_T = a__size >= 4'h2; // @[Misc.scala 205:21]
  wire  a_mask_size = a_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  a_mask_bit = a__address[1]; // @[Misc.scala 209:26]
  wire  a_mask_nbit = ~a_mask_bit; // @[Misc.scala 210:20]
  wire  a_mask_acc = _a_mask_T | a_mask_size & a_mask_nbit; // @[Misc.scala 214:29]
  wire  a_mask_acc_1 = _a_mask_T | a_mask_size & a_mask_bit; // @[Misc.scala 214:29]
  wire  a_mask_size_1 = a_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  a_mask_bit_1 = a__address[0]; // @[Misc.scala 209:26]
  wire  a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala 210:20]
  wire  a_mask_eq_2 = a_mask_nbit & a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_2 = a_mask_acc | a_mask_size_1 & a_mask_eq_2; // @[Misc.scala 214:29]
  wire  a_mask_eq_3 = a_mask_nbit & a_mask_bit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_3 = a_mask_acc | a_mask_size_1 & a_mask_eq_3; // @[Misc.scala 214:29]
  wire  a_mask_eq_4 = a_mask_bit & a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_4 = a_mask_acc_1 | a_mask_size_1 & a_mask_eq_4; // @[Misc.scala 214:29]
  wire  a_mask_eq_5 = a_mask_bit & a_mask_bit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_5 = a_mask_acc_1 | a_mask_size_1 & a_mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] a_mask = {a_mask_acc_5,a_mask_acc_4,a_mask_acc_3,a_mask_acc_2}; // @[Cat.scala 33:92]
  wire [2:0] _a_inc_tree_T = {{1'd0}, inc_trees_0_a_inc_trees_0_data}; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_3 = _a_inc_tree_T[1:0] + inc_trees_1_a_inc_trees_1_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_5 = _a_inc_tree_T_3 + inc_trees_2_a_inc_trees_2_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_7 = _a_inc_tree_T_5 + inc_trees_3_a_inc_trees_3_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_9 = _a_inc_tree_T_7 + inc_trees_4_a_inc_trees_4_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_11 = _a_inc_tree_T_9 + inc_trees_5_a_inc_trees_5_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_13 = _a_inc_tree_T_11 + inc_trees_6_a_inc_trees_6_data; // @[RAMModel.scala 112:52]
  wire [1:0] a_inc_tree = _a_inc_tree_T_13 + inc_trees_7_a_inc_trees_7_data; // @[RAMModel.scala 112:52]
  wire [2:0] _a_dec_tree_T = {{1'd0}, dec_trees_0_a_dec_trees_0_data}; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_3 = _a_dec_tree_T[1:0] + dec_trees_1_a_dec_trees_1_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_5 = _a_dec_tree_T_3 + dec_trees_2_a_dec_trees_2_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_7 = _a_dec_tree_T_5 + dec_trees_3_a_dec_trees_3_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_9 = _a_dec_tree_T_7 + dec_trees_4_a_dec_trees_4_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_11 = _a_dec_tree_T_9 + dec_trees_5_a_dec_trees_5_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_13 = _a_dec_tree_T_11 + dec_trees_6_a_dec_trees_6_data; // @[RAMModel.scala 113:52]
  wire [1:0] a_dec_tree = _a_dec_tree_T_13 + dec_trees_7_a_dec_trees_7_data; // @[RAMModel.scala 113:52]
  wire [1:0] a_inc_0 = inc_bytes_0_a_inc_bytes_0_data + a_inc_tree; // @[RAMModel.scala 114:37]
  wire [1:0] a_inc_1 = inc_bytes_1_a_inc_bytes_1_data + a_inc_tree; // @[RAMModel.scala 114:37]
  wire [1:0] a_inc_2 = inc_bytes_2_a_inc_bytes_2_data + a_inc_tree; // @[RAMModel.scala 114:37]
  wire [1:0] a_inc_3 = inc_bytes_3_a_inc_bytes_3_data + a_inc_tree; // @[RAMModel.scala 114:37]
  wire [1:0] a_dec_0 = dec_bytes_0_a_dec_bytes_0_data + a_dec_tree; // @[RAMModel.scala 115:37]
  wire [1:0] a_dec_1 = dec_bytes_1_a_dec_bytes_1_data + a_dec_tree; // @[RAMModel.scala 115:37]
  wire [1:0] a_dec_2 = dec_bytes_2_a_dec_bytes_2_data + a_dec_tree; // @[RAMModel.scala 115:37]
  wire [1:0] a_dec_3 = dec_bytes_3_a_dec_bytes_3_data + a_dec_tree; // @[RAMModel.scala 115:37]
  wire  _T_5 = ~reset; // @[RAMModel.scala 119:16]
  wire  _T_11 = a__size <= 4'h2; // @[RAMModel.scala 126:24]
  wire [3:0] _GEN_45 = a__size <= 4'h2 ? a_mask : shadow_wen_x9; // @[RAMModel.scala 126:40 127:27]
  wire [3:0] _GEN_46 = a_first & a__opcode != 3'h5 & a__opcode != 3'h4 ? _GEN_45 : shadow_wen_x9; // @[RAMModel.scala 125:87]
  wire [12:0] _GEN_47 = a_first & a__opcode != 3'h5 & a__opcode != 3'h4 ? a_sizeOH[15:3] : {{5'd0}, inc_trees_wen_x15}; // @[RAMModel.scala 125:87 129:25]
  wire  _T_12 = a__opcode == 3'h0; // @[RAMModel.scala 132:24]
  wire  _T_13 = a__opcode == 3'h1; // @[RAMModel.scala 132:63]
  wire  _T_15 = a__opcode == 3'h2; // @[RAMModel.scala 133:24]
  wire  _T_16 = a__opcode == 3'h0 | a__opcode == 3'h1 | _T_15; // @[RAMModel.scala 132:93]
  wire  _T_17 = a__opcode == 3'h3; // @[RAMModel.scala 133:66]
  wire  _T_18 = _T_16 | a__opcode == 3'h3; // @[RAMModel.scala 133:54]
  wire [1:0] _busy_T_1 = a_inc_0 - a_dec_0; // @[RAMModel.scala 136:33]
  wire  _busy_T_2 = ~a_first; // @[RAMModel.scala 136:47]
  wire [1:0] _GEN_243 = {{1'd0}, _busy_T_2}; // @[RAMModel.scala 136:44]
  wire [1:0] busy = _busy_T_1 - _GEN_243; // @[RAMModel.scala 136:44]
  wire [7:0] byte_ = a__data[7:0]; // @[RAMModel.scala 137:30]
  wire [10:0] _T_34 = {a_addr_hi, 2'h0}; // @[RAMModel.scala 144:58]
  wire [1:0] _busy_T_5 = a_inc_1 - a_dec_1; // @[RAMModel.scala 136:33]
  wire [1:0] busy_1 = _busy_T_5 - _GEN_243; // @[RAMModel.scala 136:44]
  wire [7:0] byte_1 = a__data[15:8]; // @[RAMModel.scala 137:30]
  wire [1:0] _busy_T_9 = a_inc_2 - a_dec_2; // @[RAMModel.scala 136:33]
  wire [1:0] busy_2 = _busy_T_9 - _GEN_243; // @[RAMModel.scala 136:44]
  wire [7:0] byte_2 = a__data[23:16]; // @[RAMModel.scala 137:30]
  wire [1:0] _busy_T_13 = a_inc_3 - a_dec_3; // @[RAMModel.scala 136:33]
  wire [1:0] busy_3 = _busy_T_13 - _GEN_243; // @[RAMModel.scala 136:44]
  wire [7:0] byte_3 = a__data[31:24]; // @[RAMModel.scala 137:30]
  wire [3:0] _GEN_48 = _T_16 | a__opcode == 3'h3 ? a__mask : shadow_wen_x9; // @[RAMModel.scala 133:94 134:22]
  wire  _T_95 = a__opcode == 3'h4; // @[RAMModel.scala 149:24]
  wire [25:0] _T_97 = 26'h7ff << a__size; // @[package.scala 234:77]
  wire [10:0] _T_99 = ~_T_97[10:0]; // @[package.scala 234:46]
  wire [3:0] inc_bytes_wen = a_fire ? _GEN_46 : shadow_wen_x9; // @[RAMModel.scala 117:21]
  wire [12:0] inc_trees_wen = a_fire ? _GEN_47 : {{5'd0}, inc_trees_wen_x15}; // @[RAMModel.scala 117:21]
  wire [3:0] shadow_wen = a_fire ? _GEN_48 : shadow_wen_x9; // @[RAMModel.scala 117:21]
  wire [9:0] a_waddr = wipe ? wipeIndex : {{1'd0}, a_addr_hi}; // @[RAMModel.scala 154:24]
  wire  _a_known_old_T = ~shadow_0_valid_a_shadow_0_data; // @[RAMModel.scala 156:44]
  wire  _a_known_old_T_1 = ~shadow_1_valid_a_shadow_1_data; // @[RAMModel.scala 156:44]
  wire  _a_known_old_T_2 = ~shadow_2_valid_a_shadow_2_data; // @[RAMModel.scala 156:44]
  wire  _a_known_old_T_3 = ~shadow_3_valid_a_shadow_3_data; // @[RAMModel.scala 156:44]
  wire [3:0] _a_known_old_T_4 = {_a_known_old_T_3,_a_known_old_T_2,_a_known_old_T_1,_a_known_old_T}; // @[Cat.scala 33:92]
  wire [3:0] _a_known_old_T_5 = _a_known_old_T_4 & a_mask; // @[RAMModel.scala 156:63]
  wire  a_known_old = ~(|_a_known_old_T_5); // @[RAMModel.scala 156:25]
  wire [15:0] alu_io_data_in_lo = {shadow_1_value_a_shadow_1_data,shadow_0_value_a_shadow_0_data}; // @[Cat.scala 33:92]
  wire [15:0] alu_io_data_in_hi = {shadow_3_value_a_shadow_3_data,shadow_2_value_a_shadow_2_data}; // @[Cat.scala 33:92]
  wire [15:0] a_crc_acc = a_first ? 16'h0 : crc_a_crc_acc_MPORT_data; // @[RAMModel.scala 164:26]
  wire [7:0] _a_crc_new_T_1 = a_mask[0] ? shadow_0_value_a_shadow_0_data : 8'h0; // @[RAMModel.scala 165:73]
  wire [7:0] _a_crc_new_T_3 = a_mask[1] ? shadow_1_value_a_shadow_1_data : 8'h0; // @[RAMModel.scala 165:73]
  wire [7:0] _a_crc_new_T_5 = a_mask[2] ? shadow_2_value_a_shadow_2_data : 8'h0; // @[RAMModel.scala 165:73]
  wire [7:0] _a_crc_new_T_7 = a_mask[3] ? shadow_3_value_a_shadow_3_data : 8'h0; // @[RAMModel.scala 165:73]
  wire [47:0] _a_crc_T = {a_crc_acc,_a_crc_new_T_7,_a_crc_new_T_5,_a_crc_new_T_3,_a_crc_new_T_1}; // @[Cat.scala 33:92]
  wire [47:0] _a_crc_T_6 = 48'heaa477170001 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_7 = ^_a_crc_T_6; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_8 = 48'h3fec99390002 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_9 = ^_a_crc_T_8; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_10 = 48'h7fd932720004 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_11 = ^_a_crc_T_10; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_12 = 48'h151613f30008 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_13 = ^_a_crc_T_12; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_14 = 48'h2a2c27e60010 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_15 = ^_a_crc_T_14; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_16 = 48'hbefc38db0020 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_17 = ^_a_crc_T_16; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_18 = 48'h975c06a10040 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_19 = ^_a_crc_T_18; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_20 = 48'hc41c7a550080 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_21 = ^_a_crc_T_20; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_22 = 48'h8838f4aa0100 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_23 = ^_a_crc_T_22; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_24 = 48'hfad59e430200 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_25 = ^_a_crc_T_24; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_26 = 48'hf5ab3c860400 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_27 = ^_a_crc_T_26; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_28 = 48'heb56790c0800 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_29 = ^_a_crc_T_28; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_30 = 48'hd6acf2181000 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_31 = ^_a_crc_T_30; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_32 = 48'h47fd93272000 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_33 = ^_a_crc_T_32; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_34 = 48'h8ffb264e4000 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_35 = ^_a_crc_T_34; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_36 = 48'hf5523b8b8000 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_37 = ^_a_crc_T_36; // @[CRC.scala 30:63]
  wire [7:0] a_crc_lo = {_a_crc_T_21,_a_crc_T_19,_a_crc_T_17,_a_crc_T_15,_a_crc_T_13,_a_crc_T_11,_a_crc_T_9,_a_crc_T_7}; // @[Cat.scala 33:92]
  wire [7:0] a_crc_hi = {_a_crc_T_37,_a_crc_T_35,_a_crc_T_33,_a_crc_T_31,_a_crc_T_29,_a_crc_T_27,_a_crc_T_25,_a_crc_T_23
    }; // @[Cat.scala 33:92]
  wire  _a_crc_valid_T = a_first | crc_valid_a_crc_valid_MPORT_data; // @[RAMModel.scala 167:43]
  wire  amo = _T_15 | _T_17; // @[RAMModel.scala 176:58]
  wire  _data_valid_T_4 = ~amo | a_known_old & _T_11; // @[RAMModel.scala 178:73]
  wire [1:0] _data_T_1 = inc_bytes_0_a_inc_bytes_0_data + 2'h1; // @[RAMModel.scala 186:54]
  wire [1:0] _data_T_3 = inc_bytes_1_a_inc_bytes_1_data + 2'h1; // @[RAMModel.scala 186:54]
  wire [1:0] _data_T_5 = inc_bytes_2_a_inc_bytes_2_data + 2'h1; // @[RAMModel.scala 186:54]
  wire [1:0] _data_T_7 = inc_bytes_3_a_inc_bytes_3_data + 2'h1; // @[RAMModel.scala 186:54]
  wire [1:0] _data_T_9 = inc_trees_0_a_inc_trees_0_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_11 = inc_trees_1_a_inc_trees_1_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_13 = inc_trees_2_a_inc_trees_2_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_15 = inc_trees_3_a_inc_trees_3_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_17 = inc_trees_4_a_inc_trees_4_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_19 = inc_trees_5_a_inc_trees_5_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_21 = inc_trees_6_a_inc_trees_6_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_23 = inc_trees_7_a_inc_trees_7_data + 2'h1; // @[RAMModel.scala 193:54]
  reg [2:0] d_opcode; // @[RAMModel.scala 200:22]
  reg [3:0] d_size; // @[RAMModel.scala 200:22]
  reg [1:0] d_source; // @[RAMModel.scala 200:22]
  reg  d_denied; // @[RAMModel.scala 200:22]
  reg [31:0] d_data; // @[RAMModel.scala 200:22]
  reg  d_fire; // @[RAMModel.scala 201:23]
  wire [24:0] _beats1_decode_T_5 = 25'h3ff << d_size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_7 = ~_beats1_decode_T_5[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode_1 = _beats1_decode_T_7[9:2]; // @[Edges.scala 219:59]
  wire  beats1_opdata_1 = d_opcode[0]; // @[Edges.scala 105:36]
  wire [7:0] beats1_1 = beats1_opdata_1 ? beats1_decode_1 : 8'h0; // @[Edges.scala 220:14]
  reg [7:0] counter_1; // @[Edges.scala 228:27]
  wire [7:0] counter1_1 = counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first = counter_1 == 8'h0; // @[Edges.scala 230:25]
  wire  d_last = counter_1 == 8'h1 | beats1_1 == 8'h0; // @[Edges.scala 231:37]
  wire [7:0] _count_T_1 = ~counter1_1; // @[Edges.scala 233:27]
  wire [7:0] count_1 = beats1_1 & _count_T_1; // @[Edges.scala 233:25]
  wire [9:0] d_address_inc = {count_1, 2'h0}; // @[Edges.scala 268:29]
  wire [15:0] d_sizeOH = 16'h1 << d_size; // @[OneHot.scala 57:35]
  wire [10:0] _GEN_251 = {{1'd0}, d_address_inc}; // @[RAMModel.scala 206:30]
  wire [10:0] d_address = d_flight_base | _GEN_251; // @[RAMModel.scala 206:30]
  wire [8:0] d_addr_hi = d_address[10:2]; // @[Edges.scala 191:34]
  wire  d_mask_sizeOH_shiftAmount = d_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _d_mask_sizeOH_T_1 = 2'h1 << d_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] d_mask_sizeOH = _d_mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _d_mask_T = d_size >= 4'h2; // @[Misc.scala 205:21]
  wire  d_mask_size = d_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  d_mask_bit = d_flight_base[1]; // @[Misc.scala 209:26]
  wire  d_mask_nbit = ~d_mask_bit; // @[Misc.scala 210:20]
  wire  d_mask_acc = _d_mask_T | d_mask_size & d_mask_nbit; // @[Misc.scala 214:29]
  wire  d_mask_acc_1 = _d_mask_T | d_mask_size & d_mask_bit; // @[Misc.scala 214:29]
  wire  d_mask_size_1 = d_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  d_mask_bit_1 = d_flight_base[0]; // @[Misc.scala 209:26]
  wire  d_mask_nbit_1 = ~d_mask_bit_1; // @[Misc.scala 210:20]
  wire  d_mask_eq_2 = d_mask_nbit & d_mask_nbit_1; // @[Misc.scala 213:27]
  wire  d_mask_acc_2 = d_mask_acc | d_mask_size_1 & d_mask_eq_2; // @[Misc.scala 214:29]
  wire  d_mask_eq_3 = d_mask_nbit & d_mask_bit_1; // @[Misc.scala 213:27]
  wire  d_mask_acc_3 = d_mask_acc | d_mask_size_1 & d_mask_eq_3; // @[Misc.scala 214:29]
  wire  d_mask_eq_4 = d_mask_bit & d_mask_nbit_1; // @[Misc.scala 213:27]
  wire  d_mask_acc_4 = d_mask_acc_1 | d_mask_size_1 & d_mask_eq_4; // @[Misc.scala 214:29]
  wire  d_mask_eq_5 = d_mask_bit & d_mask_bit_1; // @[Misc.scala 213:27]
  wire  d_mask_acc_5 = d_mask_acc_1 | d_mask_size_1 & d_mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] d_mask = {d_mask_acc_5,d_mask_acc_4,d_mask_acc_3,d_mask_acc_2}; // @[Cat.scala 33:92]
  wire [2:0] _d_inc_tree_T = {{1'd0}, inc_trees_0_d_inc_trees_0_data}; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_3 = _d_inc_tree_T[1:0] + inc_trees_1_d_inc_trees_1_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_5 = _d_inc_tree_T_3 + inc_trees_2_d_inc_trees_2_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_7 = _d_inc_tree_T_5 + inc_trees_3_d_inc_trees_3_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_9 = _d_inc_tree_T_7 + inc_trees_4_d_inc_trees_4_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_11 = _d_inc_tree_T_9 + inc_trees_5_d_inc_trees_5_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_13 = _d_inc_tree_T_11 + inc_trees_6_d_inc_trees_6_data; // @[RAMModel.scala 216:52]
  wire [1:0] d_inc_tree = _d_inc_tree_T_13 + inc_trees_7_d_inc_trees_7_data; // @[RAMModel.scala 216:52]
  wire [2:0] _d_dec_tree_T = {{1'd0}, dec_trees_0_d_dec_trees_0_data}; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_3 = _d_dec_tree_T[1:0] + dec_trees_1_d_dec_trees_1_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_5 = _d_dec_tree_T_3 + dec_trees_2_d_dec_trees_2_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_7 = _d_dec_tree_T_5 + dec_trees_3_d_dec_trees_3_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_9 = _d_dec_tree_T_7 + dec_trees_4_d_dec_trees_4_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_11 = _d_dec_tree_T_9 + dec_trees_5_d_dec_trees_5_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_13 = _d_dec_tree_T_11 + dec_trees_6_d_dec_trees_6_data; // @[RAMModel.scala 217:52]
  wire [1:0] d_dec_tree = _d_dec_tree_T_13 + dec_trees_7_d_dec_trees_7_data; // @[RAMModel.scala 217:52]
  wire [1:0] d_inc_0 = inc_bytes_0_d_inc_bytes_0_data + d_inc_tree; // @[RAMModel.scala 218:37]
  wire [1:0] d_inc_1 = inc_bytes_1_d_inc_bytes_1_data + d_inc_tree; // @[RAMModel.scala 218:37]
  wire [1:0] d_inc_2 = inc_bytes_2_d_inc_bytes_2_data + d_inc_tree; // @[RAMModel.scala 218:37]
  wire [1:0] d_inc_3 = inc_bytes_3_d_inc_bytes_3_data + d_inc_tree; // @[RAMModel.scala 218:37]
  wire [1:0] d_dec_0 = dec_bytes_0_d_dec_bytes_0_data + d_dec_tree; // @[RAMModel.scala 219:37]
  wire [1:0] d_dec_1 = dec_bytes_1_d_dec_bytes_1_data + d_dec_tree; // @[RAMModel.scala 219:37]
  wire [1:0] d_dec_2 = dec_bytes_2_d_dec_bytes_2_data + d_dec_tree; // @[RAMModel.scala 219:37]
  wire [1:0] d_dec_3 = dec_bytes_3_d_dec_bytes_3_data + d_dec_tree; // @[RAMModel.scala 219:37]
  reg [15:0] d_crc_reg; // @[RAMModel.scala 224:26]
  wire [15:0] d_crc_acc = d_first ? 16'h0 : d_crc_reg; // @[RAMModel.scala 225:26]
  wire [7:0] _d_crc_new_T_5 = d_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _d_crc_new_T_7 = d_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _d_crc_new_T_9 = d_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _d_crc_new_T_11 = d_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [31:0] _d_crc_new_T_12 = {_d_crc_new_T_11,_d_crc_new_T_9,_d_crc_new_T_7,_d_crc_new_T_5}; // @[Cat.scala 33:92]
  wire [31:0] d_crc_new = _d_crc_new_T_12 & d_data; // @[RAMModel.scala 226:50]
  wire [47:0] _d_crc_T = {d_crc_acc,d_crc_new}; // @[Cat.scala 33:92]
  wire [47:0] _d_crc_T_6 = 48'heaa477170001 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_7 = ^_d_crc_T_6; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_8 = 48'h3fec99390002 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_9 = ^_d_crc_T_8; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_10 = 48'h7fd932720004 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_11 = ^_d_crc_T_10; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_12 = 48'h151613f30008 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_13 = ^_d_crc_T_12; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_14 = 48'h2a2c27e60010 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_15 = ^_d_crc_T_14; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_16 = 48'hbefc38db0020 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_17 = ^_d_crc_T_16; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_18 = 48'h975c06a10040 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_19 = ^_d_crc_T_18; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_20 = 48'hc41c7a550080 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_21 = ^_d_crc_T_20; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_22 = 48'h8838f4aa0100 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_23 = ^_d_crc_T_22; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_24 = 48'hfad59e430200 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_25 = ^_d_crc_T_24; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_26 = 48'hf5ab3c860400 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_27 = ^_d_crc_T_26; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_28 = 48'heb56790c0800 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_29 = ^_d_crc_T_28; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_30 = 48'hd6acf2181000 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_31 = ^_d_crc_T_30; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_32 = 48'h47fd93272000 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_33 = ^_d_crc_T_32; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_34 = 48'h8ffb264e4000 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_35 = ^_d_crc_T_34; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_36 = 48'hf5523b8b8000 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_37 = ^_d_crc_T_36; // @[CRC.scala 30:63]
  wire [7:0] d_crc_lo = {_d_crc_T_21,_d_crc_T_19,_d_crc_T_17,_d_crc_T_15,_d_crc_T_13,_d_crc_T_11,_d_crc_T_9,_d_crc_T_7}; // @[Cat.scala 33:92]
  wire [15:0] d_crc = {_d_crc_T_37,_d_crc_T_35,_d_crc_T_33,_d_crc_T_31,_d_crc_T_29,_d_crc_T_27,_d_crc_T_25,_d_crc_T_23,
    d_crc_lo}; // @[Cat.scala 33:92]
  wire  _d_crc_valid_T = crc_valid_d_crc_valid_MPORT_data; // @[RAMModel.scala 229:28]
  reg  d_crc_valid_r; // @[Reg.scala 19:16]
  wire  _GEN_152 = d_first ? _d_crc_valid_T : d_crc_valid_r; // @[Reg.scala 19:16 20:{18,22}]
  wire [15:0] _d_crc_check_T = crc_d_crc_check_MPORT_data; // @[RAMModel.scala 230:28]
  reg [15:0] d_crc_check_r; // @[Reg.scala 19:16]
  wire [15:0] _GEN_153 = d_first ? _d_crc_check_T : d_crc_check_r; // @[Reg.scala 19:16 20:{18,22}]
  wire  _T_147 = d_flight_opcode == 3'h5; // @[RAMModel.scala 243:31]
  wire [3:0] _GEN_154 = d_size <= 4'h2 ? d_mask : shadow_wen_x9; // @[RAMModel.scala 249:40 250:27]
  wire [25:0] _d_bits_T_1 = 26'h7ff << d_size; // @[package.scala 234:77]
  wire [10:0] d_bits = ~_d_bits_T_1[10:0]; // @[package.scala 234:46]
  wire [3:0] _GEN_159 = d_last & d_flight_opcode != 3'h5 & d_flight_opcode != 3'h4 ? _GEN_154 : shadow_wen_x9; // @[RAMModel.scala 248:100]
  wire [12:0] _GEN_160 = d_last & d_flight_opcode != 3'h5 & d_flight_opcode != 3'h4 ? d_sizeOH[15:3] : {{5'd0},
    inc_trees_wen_x15}; // @[RAMModel.scala 248:100 252:25]
  wire  _T_157 = d_flight_opcode == 3'h0; // @[RAMModel.scala 265:31]
  wire  _T_158 = d_flight_opcode == 3'h1; // @[RAMModel.scala 265:77]
  wire  _T_159 = d_flight_opcode == 3'h0 | d_flight_opcode == 3'h1; // @[RAMModel.scala 265:58]
  wire  _T_179 = d_flight_opcode == 3'h4; // @[RAMModel.scala 273:31]
  wire  _T_180 = d_flight_opcode == 3'h2; // @[RAMModel.scala 273:69]
  wire  _T_182 = d_flight_opcode == 3'h3; // @[RAMModel.scala 273:118]
  wire  _T_183 = d_flight_opcode == 3'h4 | d_flight_opcode == 3'h2 | d_flight_opcode == 3'h3; // @[RAMModel.scala 273:99]
  wire [7:0] got = d_data[7:0]; // @[RAMModel.scala 276:29]
  wire [10:0] d_addr = {d_addr_hi, 2'h0}; // @[RAMModel.scala 279:38]
  wire  shadow_valid = shadow_0_valid_d_shadow_0_data;
  wire  _T_202 = ~shadow_valid; // @[RAMModel.scala 285:21]
  wire  _T_205 = d_inc_0 != d_dec_0; // @[RAMModel.scala 287:37]
  wire [7:0] shadow_value = shadow_0_value_d_shadow_0_data;
  wire [7:0] got_1 = d_data[15:8]; // @[RAMModel.scala 276:29]
  wire [10:0] d_addr_1 = d_addr | 11'h1; // @[RAMModel.scala 279:47]
  wire  shadow_4_valid = shadow_1_valid_d_shadow_1_data;
  wire  _T_244 = ~shadow_4_valid; // @[RAMModel.scala 285:21]
  wire  _T_247 = d_inc_1 != d_dec_1; // @[RAMModel.scala 287:37]
  wire [7:0] shadow_4_value = shadow_1_value_d_shadow_1_data;
  wire [7:0] got_2 = d_data[23:16]; // @[RAMModel.scala 276:29]
  wire [10:0] d_addr_2 = d_addr | 11'h2; // @[RAMModel.scala 279:47]
  wire  shadow_5_valid = shadow_2_valid_d_shadow_2_data;
  wire  _T_286 = ~shadow_5_valid; // @[RAMModel.scala 285:21]
  wire  _T_289 = d_inc_2 != d_dec_2; // @[RAMModel.scala 287:37]
  wire [7:0] shadow_5_value = shadow_2_value_d_shadow_2_data;
  wire [7:0] got_3 = d_data[31:24]; // @[RAMModel.scala 276:29]
  wire [10:0] d_addr_3 = d_addr | 11'h3; // @[RAMModel.scala 279:47]
  wire  shadow_6_valid = shadow_3_valid_d_shadow_3_data;
  wire  _T_328 = ~shadow_6_valid; // @[RAMModel.scala 285:21]
  wire  _T_331 = d_inc_3 != d_dec_3; // @[RAMModel.scala 287:37]
  wire [7:0] shadow_6_value = shadow_3_value_d_shadow_3_data;
  wire  _T_358 = _T_180 | _T_182; // @[RAMModel.scala 304:61]
  wire  _T_364 = ~d_denied; // @[RAMModel.scala 312:19]
  wire [3:0] dec_bytes_wen = d_fire ? _GEN_159 : shadow_wen_x9; // @[RAMModel.scala 235:21]
  wire [12:0] dec_trees_wen = d_fire ? _GEN_160 : {{5'd0}, inc_trees_wen_x15}; // @[RAMModel.scala 235:21]
  wire [9:0] d_waddr = wipe ? wipeIndex : {{1'd0}, d_addr_hi}; // @[RAMModel.scala 318:24]
  wire [1:0] _data_T_25 = dec_bytes_0_d_dec_bytes_0_data + 2'h1; // @[RAMModel.scala 320:54]
  wire [1:0] _data_T_27 = dec_bytes_1_d_dec_bytes_1_data + 2'h1; // @[RAMModel.scala 320:54]
  wire [1:0] _data_T_29 = dec_bytes_2_d_dec_bytes_2_data + 2'h1; // @[RAMModel.scala 320:54]
  wire [1:0] _data_T_31 = dec_bytes_3_d_dec_bytes_3_data + 2'h1; // @[RAMModel.scala 320:54]
  wire [1:0] _data_T_33 = dec_trees_0_d_dec_trees_0_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_35 = dec_trees_1_d_dec_trees_1_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_37 = dec_trees_2_d_dec_trees_2_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_39 = dec_trees_3_d_dec_trees_3_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_41 = dec_trees_4_d_dec_trees_4_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_43 = dec_trees_5_d_dec_trees_5_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_45 = dec_trees_6_d_dec_trees_6_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_47 = dec_trees_7_d_dec_trees_7_data + 2'h1; // @[RAMModel.scala 327:54]
  wire  _GEN_256 = a_fire & _T_18 & a__mask[0]; // @[RAMModel.scala 139:21]
  wire  _GEN_272 = a_fire & _T_18 & a__mask[1]; // @[RAMModel.scala 139:21]
  wire  _GEN_288 = a_fire & _T_18 & a__mask[2]; // @[RAMModel.scala 139:21]
  wire  _GEN_304 = a_fire & _T_18 & a__mask[3]; // @[RAMModel.scala 139:21]
  wire  _GEN_328 = d_fire & _T_159; // @[RAMModel.scala 266:18]
  wire  _GEN_339 = d_fire & _T_183; // @[RAMModel.scala 274:18]
  wire  _GEN_345 = _GEN_339 & d_mask[0]; // @[RAMModel.scala 280:21]
  wire  _GEN_363 = _GEN_345 & ~_T_202; // @[RAMModel.scala 288:23]
  wire  _GEN_370 = _GEN_363 & ~_T_205; // @[RAMModel.scala 292:23]
  wire  _GEN_379 = _GEN_370 & _T_364; // @[RAMModel.scala 296:23]
  wire  _GEN_409 = _GEN_339 & d_mask[1]; // @[RAMModel.scala 280:21]
  wire  _GEN_427 = _GEN_409 & ~_T_244; // @[RAMModel.scala 288:23]
  wire  _GEN_434 = _GEN_427 & ~_T_247; // @[RAMModel.scala 292:23]
  wire  _GEN_443 = _GEN_434 & _T_364; // @[RAMModel.scala 296:23]
  wire  _GEN_473 = _GEN_339 & d_mask[2]; // @[RAMModel.scala 280:21]
  wire  _GEN_491 = _GEN_473 & ~_T_286; // @[RAMModel.scala 288:23]
  wire  _GEN_498 = _GEN_491 & ~_T_289; // @[RAMModel.scala 292:23]
  wire  _GEN_507 = _GEN_498 & _T_364; // @[RAMModel.scala 296:23]
  wire  _GEN_537 = _GEN_339 & d_mask[3]; // @[RAMModel.scala 280:21]
  wire  _GEN_555 = _GEN_537 & ~_T_328; // @[RAMModel.scala 288:23]
  wire  _GEN_562 = _GEN_555 & ~_T_331; // @[RAMModel.scala 292:23]
  wire  _GEN_571 = _GEN_562 & _T_364; // @[RAMModel.scala 296:23]
  wire  _GEN_601 = d_fire & _T_358 & d_last; // @[RAMModel.scala 311:19]
  TLMonitor_1 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Atomics alu ( // @[RAMModel.scala 157:23]
    .io_a_opcode(alu_io_a_opcode),
    .io_a_mask(alu_io_a_mask),
    .io_a_data(alu_io_a_data),
    .io_data_in(alu_io_data_in),
    .io_data_out(alu_io_data_out)
  );
  assign shadow_0_valid_a_shadow_0_en = 1'h1;
  assign shadow_0_valid_a_shadow_0_addr = a_waddr[8:0];
  assign shadow_0_valid_a_shadow_0_data = shadow_0_valid[shadow_0_valid_a_shadow_0_addr]; // @[RAMModel.scala 69:45]
  assign shadow_0_valid_d_shadow_0_en = 1'h1;
  assign shadow_0_valid_d_shadow_0_addr = d_address[10:2];
  assign shadow_0_valid_d_shadow_0_data = shadow_0_valid[shadow_0_valid_d_shadow_0_addr]; // @[RAMModel.scala 69:45]
  assign shadow_0_valid_MPORT_2_data = wipe ? 1'h0 : _data_valid_T_4;
  assign shadow_0_valid_MPORT_2_addr = a_waddr[8:0];
  assign shadow_0_valid_MPORT_2_mask = 1'h1;
  assign shadow_0_valid_MPORT_2_en = shadow_wen[0];
  assign shadow_0_value_a_shadow_0_en = 1'h1;
  assign shadow_0_value_a_shadow_0_addr = a_waddr[8:0];
  assign shadow_0_value_a_shadow_0_data = shadow_0_value[shadow_0_value_a_shadow_0_addr]; // @[RAMModel.scala 69:45]
  assign shadow_0_value_d_shadow_0_en = 1'h1;
  assign shadow_0_value_d_shadow_0_addr = d_address[10:2];
  assign shadow_0_value_d_shadow_0_data = shadow_0_value[shadow_0_value_d_shadow_0_addr]; // @[RAMModel.scala 69:45]
  assign shadow_0_value_MPORT_2_data = alu_io_data_out[7:0];
  assign shadow_0_value_MPORT_2_addr = a_waddr[8:0];
  assign shadow_0_value_MPORT_2_mask = 1'h1;
  assign shadow_0_value_MPORT_2_en = shadow_wen[0];
  assign shadow_1_valid_a_shadow_1_en = 1'h1;
  assign shadow_1_valid_a_shadow_1_addr = a_waddr[8:0];
  assign shadow_1_valid_a_shadow_1_data = shadow_1_valid[shadow_1_valid_a_shadow_1_addr]; // @[RAMModel.scala 69:45]
  assign shadow_1_valid_d_shadow_1_en = 1'h1;
  assign shadow_1_valid_d_shadow_1_addr = d_address[10:2];
  assign shadow_1_valid_d_shadow_1_data = shadow_1_valid[shadow_1_valid_d_shadow_1_addr]; // @[RAMModel.scala 69:45]
  assign shadow_1_valid_MPORT_3_data = wipe ? 1'h0 : _data_valid_T_4;
  assign shadow_1_valid_MPORT_3_addr = a_waddr[8:0];
  assign shadow_1_valid_MPORT_3_mask = 1'h1;
  assign shadow_1_valid_MPORT_3_en = shadow_wen[1];
  assign shadow_1_value_a_shadow_1_en = 1'h1;
  assign shadow_1_value_a_shadow_1_addr = a_waddr[8:0];
  assign shadow_1_value_a_shadow_1_data = shadow_1_value[shadow_1_value_a_shadow_1_addr]; // @[RAMModel.scala 69:45]
  assign shadow_1_value_d_shadow_1_en = 1'h1;
  assign shadow_1_value_d_shadow_1_addr = d_address[10:2];
  assign shadow_1_value_d_shadow_1_data = shadow_1_value[shadow_1_value_d_shadow_1_addr]; // @[RAMModel.scala 69:45]
  assign shadow_1_value_MPORT_3_data = alu_io_data_out[15:8];
  assign shadow_1_value_MPORT_3_addr = a_waddr[8:0];
  assign shadow_1_value_MPORT_3_mask = 1'h1;
  assign shadow_1_value_MPORT_3_en = shadow_wen[1];
  assign shadow_2_valid_a_shadow_2_en = 1'h1;
  assign shadow_2_valid_a_shadow_2_addr = a_waddr[8:0];
  assign shadow_2_valid_a_shadow_2_data = shadow_2_valid[shadow_2_valid_a_shadow_2_addr]; // @[RAMModel.scala 69:45]
  assign shadow_2_valid_d_shadow_2_en = 1'h1;
  assign shadow_2_valid_d_shadow_2_addr = d_address[10:2];
  assign shadow_2_valid_d_shadow_2_data = shadow_2_valid[shadow_2_valid_d_shadow_2_addr]; // @[RAMModel.scala 69:45]
  assign shadow_2_valid_MPORT_4_data = wipe ? 1'h0 : _data_valid_T_4;
  assign shadow_2_valid_MPORT_4_addr = a_waddr[8:0];
  assign shadow_2_valid_MPORT_4_mask = 1'h1;
  assign shadow_2_valid_MPORT_4_en = shadow_wen[2];
  assign shadow_2_value_a_shadow_2_en = 1'h1;
  assign shadow_2_value_a_shadow_2_addr = a_waddr[8:0];
  assign shadow_2_value_a_shadow_2_data = shadow_2_value[shadow_2_value_a_shadow_2_addr]; // @[RAMModel.scala 69:45]
  assign shadow_2_value_d_shadow_2_en = 1'h1;
  assign shadow_2_value_d_shadow_2_addr = d_address[10:2];
  assign shadow_2_value_d_shadow_2_data = shadow_2_value[shadow_2_value_d_shadow_2_addr]; // @[RAMModel.scala 69:45]
  assign shadow_2_value_MPORT_4_data = alu_io_data_out[23:16];
  assign shadow_2_value_MPORT_4_addr = a_waddr[8:0];
  assign shadow_2_value_MPORT_4_mask = 1'h1;
  assign shadow_2_value_MPORT_4_en = shadow_wen[2];
  assign shadow_3_valid_a_shadow_3_en = 1'h1;
  assign shadow_3_valid_a_shadow_3_addr = a_waddr[8:0];
  assign shadow_3_valid_a_shadow_3_data = shadow_3_valid[shadow_3_valid_a_shadow_3_addr]; // @[RAMModel.scala 69:45]
  assign shadow_3_valid_d_shadow_3_en = 1'h1;
  assign shadow_3_valid_d_shadow_3_addr = d_address[10:2];
  assign shadow_3_valid_d_shadow_3_data = shadow_3_valid[shadow_3_valid_d_shadow_3_addr]; // @[RAMModel.scala 69:45]
  assign shadow_3_valid_MPORT_5_data = wipe ? 1'h0 : _data_valid_T_4;
  assign shadow_3_valid_MPORT_5_addr = a_waddr[8:0];
  assign shadow_3_valid_MPORT_5_mask = 1'h1;
  assign shadow_3_valid_MPORT_5_en = shadow_wen[3];
  assign shadow_3_value_a_shadow_3_en = 1'h1;
  assign shadow_3_value_a_shadow_3_addr = a_waddr[8:0];
  assign shadow_3_value_a_shadow_3_data = shadow_3_value[shadow_3_value_a_shadow_3_addr]; // @[RAMModel.scala 69:45]
  assign shadow_3_value_d_shadow_3_en = 1'h1;
  assign shadow_3_value_d_shadow_3_addr = d_address[10:2];
  assign shadow_3_value_d_shadow_3_data = shadow_3_value[shadow_3_value_d_shadow_3_addr]; // @[RAMModel.scala 69:45]
  assign shadow_3_value_MPORT_5_data = alu_io_data_out[31:24];
  assign shadow_3_value_MPORT_5_addr = a_waddr[8:0];
  assign shadow_3_value_MPORT_5_mask = 1'h1;
  assign shadow_3_value_MPORT_5_en = shadow_wen[3];
  assign inc_bytes_0_a_inc_bytes_0_en = 1'h1;
  assign inc_bytes_0_a_inc_bytes_0_addr = a_address[10:2];
  assign inc_bytes_0_a_inc_bytes_0_data = inc_bytes_0[inc_bytes_0_a_inc_bytes_0_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_0_d_inc_bytes_0_en = 1'h1;
  assign inc_bytes_0_d_inc_bytes_0_addr = d_address[10:2];
  assign inc_bytes_0_d_inc_bytes_0_data = inc_bytes_0[inc_bytes_0_d_inc_bytes_0_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_0_MPORT_6_data = wipe ? 2'h0 : _data_T_1;
  assign inc_bytes_0_MPORT_6_addr = a_waddr[8:0];
  assign inc_bytes_0_MPORT_6_mask = 1'h1;
  assign inc_bytes_0_MPORT_6_en = inc_bytes_wen[0];
  assign inc_bytes_1_a_inc_bytes_1_en = 1'h1;
  assign inc_bytes_1_a_inc_bytes_1_addr = a_address[10:2];
  assign inc_bytes_1_a_inc_bytes_1_data = inc_bytes_1[inc_bytes_1_a_inc_bytes_1_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_1_d_inc_bytes_1_en = 1'h1;
  assign inc_bytes_1_d_inc_bytes_1_addr = d_address[10:2];
  assign inc_bytes_1_d_inc_bytes_1_data = inc_bytes_1[inc_bytes_1_d_inc_bytes_1_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_1_MPORT_7_data = wipe ? 2'h0 : _data_T_3;
  assign inc_bytes_1_MPORT_7_addr = a_waddr[8:0];
  assign inc_bytes_1_MPORT_7_mask = 1'h1;
  assign inc_bytes_1_MPORT_7_en = inc_bytes_wen[1];
  assign inc_bytes_2_a_inc_bytes_2_en = 1'h1;
  assign inc_bytes_2_a_inc_bytes_2_addr = a_address[10:2];
  assign inc_bytes_2_a_inc_bytes_2_data = inc_bytes_2[inc_bytes_2_a_inc_bytes_2_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_2_d_inc_bytes_2_en = 1'h1;
  assign inc_bytes_2_d_inc_bytes_2_addr = d_address[10:2];
  assign inc_bytes_2_d_inc_bytes_2_data = inc_bytes_2[inc_bytes_2_d_inc_bytes_2_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_2_MPORT_8_data = wipe ? 2'h0 : _data_T_5;
  assign inc_bytes_2_MPORT_8_addr = a_waddr[8:0];
  assign inc_bytes_2_MPORT_8_mask = 1'h1;
  assign inc_bytes_2_MPORT_8_en = inc_bytes_wen[2];
  assign inc_bytes_3_a_inc_bytes_3_en = 1'h1;
  assign inc_bytes_3_a_inc_bytes_3_addr = a_address[10:2];
  assign inc_bytes_3_a_inc_bytes_3_data = inc_bytes_3[inc_bytes_3_a_inc_bytes_3_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_3_d_inc_bytes_3_en = 1'h1;
  assign inc_bytes_3_d_inc_bytes_3_addr = d_address[10:2];
  assign inc_bytes_3_d_inc_bytes_3_data = inc_bytes_3[inc_bytes_3_d_inc_bytes_3_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_3_MPORT_9_data = wipe ? 2'h0 : _data_T_7;
  assign inc_bytes_3_MPORT_9_addr = a_waddr[8:0];
  assign inc_bytes_3_MPORT_9_mask = 1'h1;
  assign inc_bytes_3_MPORT_9_en = inc_bytes_wen[3];
  assign dec_bytes_0_a_dec_bytes_0_en = 1'h1;
  assign dec_bytes_0_a_dec_bytes_0_addr = a_address[10:2];
  assign dec_bytes_0_a_dec_bytes_0_data = dec_bytes_0[dec_bytes_0_a_dec_bytes_0_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_0_d_dec_bytes_0_en = 1'h1;
  assign dec_bytes_0_d_dec_bytes_0_addr = d_address[10:2];
  assign dec_bytes_0_d_dec_bytes_0_data = dec_bytes_0[dec_bytes_0_d_dec_bytes_0_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_0_MPORT_18_data = wipe ? 2'h0 : _data_T_25;
  assign dec_bytes_0_MPORT_18_addr = d_waddr[8:0];
  assign dec_bytes_0_MPORT_18_mask = 1'h1;
  assign dec_bytes_0_MPORT_18_en = dec_bytes_wen[0];
  assign dec_bytes_1_a_dec_bytes_1_en = 1'h1;
  assign dec_bytes_1_a_dec_bytes_1_addr = a_address[10:2];
  assign dec_bytes_1_a_dec_bytes_1_data = dec_bytes_1[dec_bytes_1_a_dec_bytes_1_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_1_d_dec_bytes_1_en = 1'h1;
  assign dec_bytes_1_d_dec_bytes_1_addr = d_address[10:2];
  assign dec_bytes_1_d_dec_bytes_1_data = dec_bytes_1[dec_bytes_1_d_dec_bytes_1_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_1_MPORT_19_data = wipe ? 2'h0 : _data_T_27;
  assign dec_bytes_1_MPORT_19_addr = d_waddr[8:0];
  assign dec_bytes_1_MPORT_19_mask = 1'h1;
  assign dec_bytes_1_MPORT_19_en = dec_bytes_wen[1];
  assign dec_bytes_2_a_dec_bytes_2_en = 1'h1;
  assign dec_bytes_2_a_dec_bytes_2_addr = a_address[10:2];
  assign dec_bytes_2_a_dec_bytes_2_data = dec_bytes_2[dec_bytes_2_a_dec_bytes_2_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_2_d_dec_bytes_2_en = 1'h1;
  assign dec_bytes_2_d_dec_bytes_2_addr = d_address[10:2];
  assign dec_bytes_2_d_dec_bytes_2_data = dec_bytes_2[dec_bytes_2_d_dec_bytes_2_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_2_MPORT_20_data = wipe ? 2'h0 : _data_T_29;
  assign dec_bytes_2_MPORT_20_addr = d_waddr[8:0];
  assign dec_bytes_2_MPORT_20_mask = 1'h1;
  assign dec_bytes_2_MPORT_20_en = dec_bytes_wen[2];
  assign dec_bytes_3_a_dec_bytes_3_en = 1'h1;
  assign dec_bytes_3_a_dec_bytes_3_addr = a_address[10:2];
  assign dec_bytes_3_a_dec_bytes_3_data = dec_bytes_3[dec_bytes_3_a_dec_bytes_3_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_3_d_dec_bytes_3_en = 1'h1;
  assign dec_bytes_3_d_dec_bytes_3_addr = d_address[10:2];
  assign dec_bytes_3_d_dec_bytes_3_data = dec_bytes_3[dec_bytes_3_d_dec_bytes_3_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_3_MPORT_21_data = wipe ? 2'h0 : _data_T_31;
  assign dec_bytes_3_MPORT_21_addr = d_waddr[8:0];
  assign dec_bytes_3_MPORT_21_mask = 1'h1;
  assign dec_bytes_3_MPORT_21_en = dec_bytes_wen[3];
  assign inc_trees_0_a_inc_trees_0_en = 1'h1;
  assign inc_trees_0_a_inc_trees_0_addr = a_addr_hi[8:1];
  assign inc_trees_0_a_inc_trees_0_data = inc_trees_0[inc_trees_0_a_inc_trees_0_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_0_d_inc_trees_0_en = 1'h1;
  assign inc_trees_0_d_inc_trees_0_addr = d_addr_hi[8:1];
  assign inc_trees_0_d_inc_trees_0_data = inc_trees_0[inc_trees_0_d_inc_trees_0_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_0_MPORT_10_data = wipe ? 2'h0 : _data_T_9;
  assign inc_trees_0_MPORT_10_addr = a_waddr[8:1];
  assign inc_trees_0_MPORT_10_mask = 1'h1;
  assign inc_trees_0_MPORT_10_en = inc_trees_wen[0];
  assign inc_trees_1_a_inc_trees_1_en = 1'h1;
  assign inc_trees_1_a_inc_trees_1_addr = a_addr_hi[8:2];
  assign inc_trees_1_a_inc_trees_1_data = inc_trees_1[inc_trees_1_a_inc_trees_1_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_1_d_inc_trees_1_en = 1'h1;
  assign inc_trees_1_d_inc_trees_1_addr = d_addr_hi[8:2];
  assign inc_trees_1_d_inc_trees_1_data = inc_trees_1[inc_trees_1_d_inc_trees_1_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_1_MPORT_11_data = wipe ? 2'h0 : _data_T_11;
  assign inc_trees_1_MPORT_11_addr = a_waddr[8:2];
  assign inc_trees_1_MPORT_11_mask = 1'h1;
  assign inc_trees_1_MPORT_11_en = inc_trees_wen[1];
  assign inc_trees_2_a_inc_trees_2_en = 1'h1;
  assign inc_trees_2_a_inc_trees_2_addr = a_addr_hi[8:3];
  assign inc_trees_2_a_inc_trees_2_data = inc_trees_2[inc_trees_2_a_inc_trees_2_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_2_d_inc_trees_2_en = 1'h1;
  assign inc_trees_2_d_inc_trees_2_addr = d_addr_hi[8:3];
  assign inc_trees_2_d_inc_trees_2_data = inc_trees_2[inc_trees_2_d_inc_trees_2_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_2_MPORT_12_data = wipe ? 2'h0 : _data_T_13;
  assign inc_trees_2_MPORT_12_addr = a_waddr[8:3];
  assign inc_trees_2_MPORT_12_mask = 1'h1;
  assign inc_trees_2_MPORT_12_en = inc_trees_wen[2];
  assign inc_trees_3_a_inc_trees_3_en = 1'h1;
  assign inc_trees_3_a_inc_trees_3_addr = a_addr_hi[8:4];
  assign inc_trees_3_a_inc_trees_3_data = inc_trees_3[inc_trees_3_a_inc_trees_3_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_3_d_inc_trees_3_en = 1'h1;
  assign inc_trees_3_d_inc_trees_3_addr = d_addr_hi[8:4];
  assign inc_trees_3_d_inc_trees_3_data = inc_trees_3[inc_trees_3_d_inc_trees_3_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_3_MPORT_13_data = wipe ? 2'h0 : _data_T_15;
  assign inc_trees_3_MPORT_13_addr = a_waddr[8:4];
  assign inc_trees_3_MPORT_13_mask = 1'h1;
  assign inc_trees_3_MPORT_13_en = inc_trees_wen[3];
  assign inc_trees_4_a_inc_trees_4_en = 1'h1;
  assign inc_trees_4_a_inc_trees_4_addr = a_addr_hi[8:5];
  assign inc_trees_4_a_inc_trees_4_data = inc_trees_4[inc_trees_4_a_inc_trees_4_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_4_d_inc_trees_4_en = 1'h1;
  assign inc_trees_4_d_inc_trees_4_addr = d_addr_hi[8:5];
  assign inc_trees_4_d_inc_trees_4_data = inc_trees_4[inc_trees_4_d_inc_trees_4_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_4_MPORT_14_data = wipe ? 2'h0 : _data_T_17;
  assign inc_trees_4_MPORT_14_addr = a_waddr[8:5];
  assign inc_trees_4_MPORT_14_mask = 1'h1;
  assign inc_trees_4_MPORT_14_en = inc_trees_wen[4];
  assign inc_trees_5_a_inc_trees_5_en = 1'h1;
  assign inc_trees_5_a_inc_trees_5_addr = a_addr_hi[8:6];
  assign inc_trees_5_a_inc_trees_5_data = inc_trees_5[inc_trees_5_a_inc_trees_5_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_5_d_inc_trees_5_en = 1'h1;
  assign inc_trees_5_d_inc_trees_5_addr = d_addr_hi[8:6];
  assign inc_trees_5_d_inc_trees_5_data = inc_trees_5[inc_trees_5_d_inc_trees_5_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_5_MPORT_15_data = wipe ? 2'h0 : _data_T_19;
  assign inc_trees_5_MPORT_15_addr = a_waddr[8:6];
  assign inc_trees_5_MPORT_15_mask = 1'h1;
  assign inc_trees_5_MPORT_15_en = inc_trees_wen[5];
  assign inc_trees_6_a_inc_trees_6_en = 1'h1;
  assign inc_trees_6_a_inc_trees_6_addr = a_addr_hi[8:7];
  assign inc_trees_6_a_inc_trees_6_data = inc_trees_6[inc_trees_6_a_inc_trees_6_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_6_d_inc_trees_6_en = 1'h1;
  assign inc_trees_6_d_inc_trees_6_addr = d_addr_hi[8:7];
  assign inc_trees_6_d_inc_trees_6_data = inc_trees_6[inc_trees_6_d_inc_trees_6_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_6_MPORT_16_data = wipe ? 2'h0 : _data_T_21;
  assign inc_trees_6_MPORT_16_addr = a_waddr[8:7];
  assign inc_trees_6_MPORT_16_mask = 1'h1;
  assign inc_trees_6_MPORT_16_en = inc_trees_wen[6];
  assign inc_trees_7_a_inc_trees_7_en = 1'h1;
  assign inc_trees_7_a_inc_trees_7_addr = a_addr_hi[8];
  assign inc_trees_7_a_inc_trees_7_data = inc_trees_7[inc_trees_7_a_inc_trees_7_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_7_d_inc_trees_7_en = 1'h1;
  assign inc_trees_7_d_inc_trees_7_addr = d_addr_hi[8];
  assign inc_trees_7_d_inc_trees_7_data = inc_trees_7[inc_trees_7_d_inc_trees_7_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_7_MPORT_17_data = wipe ? 2'h0 : _data_T_23;
  assign inc_trees_7_MPORT_17_addr = a_waddr[8];
  assign inc_trees_7_MPORT_17_mask = 1'h1;
  assign inc_trees_7_MPORT_17_en = inc_trees_wen[7];
  assign dec_trees_0_a_dec_trees_0_en = 1'h1;
  assign dec_trees_0_a_dec_trees_0_addr = a_addr_hi[8:1];
  assign dec_trees_0_a_dec_trees_0_data = dec_trees_0[dec_trees_0_a_dec_trees_0_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_0_d_dec_trees_0_en = 1'h1;
  assign dec_trees_0_d_dec_trees_0_addr = d_addr_hi[8:1];
  assign dec_trees_0_d_dec_trees_0_data = dec_trees_0[dec_trees_0_d_dec_trees_0_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_0_MPORT_22_data = wipe ? 2'h0 : _data_T_33;
  assign dec_trees_0_MPORT_22_addr = d_waddr[8:1];
  assign dec_trees_0_MPORT_22_mask = 1'h1;
  assign dec_trees_0_MPORT_22_en = dec_trees_wen[0];
  assign dec_trees_1_a_dec_trees_1_en = 1'h1;
  assign dec_trees_1_a_dec_trees_1_addr = a_addr_hi[8:2];
  assign dec_trees_1_a_dec_trees_1_data = dec_trees_1[dec_trees_1_a_dec_trees_1_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_1_d_dec_trees_1_en = 1'h1;
  assign dec_trees_1_d_dec_trees_1_addr = d_addr_hi[8:2];
  assign dec_trees_1_d_dec_trees_1_data = dec_trees_1[dec_trees_1_d_dec_trees_1_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_1_MPORT_23_data = wipe ? 2'h0 : _data_T_35;
  assign dec_trees_1_MPORT_23_addr = d_waddr[8:2];
  assign dec_trees_1_MPORT_23_mask = 1'h1;
  assign dec_trees_1_MPORT_23_en = dec_trees_wen[1];
  assign dec_trees_2_a_dec_trees_2_en = 1'h1;
  assign dec_trees_2_a_dec_trees_2_addr = a_addr_hi[8:3];
  assign dec_trees_2_a_dec_trees_2_data = dec_trees_2[dec_trees_2_a_dec_trees_2_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_2_d_dec_trees_2_en = 1'h1;
  assign dec_trees_2_d_dec_trees_2_addr = d_addr_hi[8:3];
  assign dec_trees_2_d_dec_trees_2_data = dec_trees_2[dec_trees_2_d_dec_trees_2_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_2_MPORT_24_data = wipe ? 2'h0 : _data_T_37;
  assign dec_trees_2_MPORT_24_addr = d_waddr[8:3];
  assign dec_trees_2_MPORT_24_mask = 1'h1;
  assign dec_trees_2_MPORT_24_en = dec_trees_wen[2];
  assign dec_trees_3_a_dec_trees_3_en = 1'h1;
  assign dec_trees_3_a_dec_trees_3_addr = a_addr_hi[8:4];
  assign dec_trees_3_a_dec_trees_3_data = dec_trees_3[dec_trees_3_a_dec_trees_3_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_3_d_dec_trees_3_en = 1'h1;
  assign dec_trees_3_d_dec_trees_3_addr = d_addr_hi[8:4];
  assign dec_trees_3_d_dec_trees_3_data = dec_trees_3[dec_trees_3_d_dec_trees_3_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_3_MPORT_25_data = wipe ? 2'h0 : _data_T_39;
  assign dec_trees_3_MPORT_25_addr = d_waddr[8:4];
  assign dec_trees_3_MPORT_25_mask = 1'h1;
  assign dec_trees_3_MPORT_25_en = dec_trees_wen[3];
  assign dec_trees_4_a_dec_trees_4_en = 1'h1;
  assign dec_trees_4_a_dec_trees_4_addr = a_addr_hi[8:5];
  assign dec_trees_4_a_dec_trees_4_data = dec_trees_4[dec_trees_4_a_dec_trees_4_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_4_d_dec_trees_4_en = 1'h1;
  assign dec_trees_4_d_dec_trees_4_addr = d_addr_hi[8:5];
  assign dec_trees_4_d_dec_trees_4_data = dec_trees_4[dec_trees_4_d_dec_trees_4_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_4_MPORT_26_data = wipe ? 2'h0 : _data_T_41;
  assign dec_trees_4_MPORT_26_addr = d_waddr[8:5];
  assign dec_trees_4_MPORT_26_mask = 1'h1;
  assign dec_trees_4_MPORT_26_en = dec_trees_wen[4];
  assign dec_trees_5_a_dec_trees_5_en = 1'h1;
  assign dec_trees_5_a_dec_trees_5_addr = a_addr_hi[8:6];
  assign dec_trees_5_a_dec_trees_5_data = dec_trees_5[dec_trees_5_a_dec_trees_5_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_5_d_dec_trees_5_en = 1'h1;
  assign dec_trees_5_d_dec_trees_5_addr = d_addr_hi[8:6];
  assign dec_trees_5_d_dec_trees_5_data = dec_trees_5[dec_trees_5_d_dec_trees_5_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_5_MPORT_27_data = wipe ? 2'h0 : _data_T_43;
  assign dec_trees_5_MPORT_27_addr = d_waddr[8:6];
  assign dec_trees_5_MPORT_27_mask = 1'h1;
  assign dec_trees_5_MPORT_27_en = dec_trees_wen[5];
  assign dec_trees_6_a_dec_trees_6_en = 1'h1;
  assign dec_trees_6_a_dec_trees_6_addr = a_addr_hi[8:7];
  assign dec_trees_6_a_dec_trees_6_data = dec_trees_6[dec_trees_6_a_dec_trees_6_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_6_d_dec_trees_6_en = 1'h1;
  assign dec_trees_6_d_dec_trees_6_addr = d_addr_hi[8:7];
  assign dec_trees_6_d_dec_trees_6_data = dec_trees_6[dec_trees_6_d_dec_trees_6_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_6_MPORT_28_data = wipe ? 2'h0 : _data_T_45;
  assign dec_trees_6_MPORT_28_addr = d_waddr[8:7];
  assign dec_trees_6_MPORT_28_mask = 1'h1;
  assign dec_trees_6_MPORT_28_en = dec_trees_wen[6];
  assign dec_trees_7_a_dec_trees_7_en = 1'h1;
  assign dec_trees_7_a_dec_trees_7_addr = a_addr_hi[8];
  assign dec_trees_7_a_dec_trees_7_data = dec_trees_7[dec_trees_7_a_dec_trees_7_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_7_d_dec_trees_7_en = 1'h1;
  assign dec_trees_7_d_dec_trees_7_addr = d_addr_hi[8];
  assign dec_trees_7_d_dec_trees_7_data = dec_trees_7[dec_trees_7_d_dec_trees_7_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_7_MPORT_29_data = wipe ? 2'h0 : _data_T_47;
  assign dec_trees_7_MPORT_29_addr = d_waddr[8];
  assign dec_trees_7_MPORT_29_mask = 1'h1;
  assign dec_trees_7_MPORT_29_en = dec_trees_wen[7];
  assign crc_a_crc_acc_MPORT_en = 1'h1;
  assign crc_a_crc_acc_MPORT_addr = a__source;
  assign crc_a_crc_acc_MPORT_data = crc[crc_a_crc_acc_MPORT_addr]; // @[RAMModel.scala 162:20]
  assign crc_d_crc_check_MPORT_en = 1'h1;
  assign crc_d_crc_check_MPORT_addr = d_source;
  assign crc_d_crc_check_MPORT_data = crc[crc_d_crc_check_MPORT_addr]; // @[RAMModel.scala 162:20]
  assign crc_MPORT_data = {a_crc_hi,a_crc_lo};
  assign crc_MPORT_addr = a__source;
  assign crc_MPORT_mask = 1'h1;
  assign crc_MPORT_en = a_fire;
  assign crc_valid_a_crc_valid_MPORT_en = 1'h1;
  assign crc_valid_a_crc_valid_MPORT_addr = a__source;
  assign crc_valid_a_crc_valid_MPORT_data = crc_valid[crc_valid_a_crc_valid_MPORT_addr]; // @[RAMModel.scala 163:26]
  assign crc_valid_d_crc_valid_MPORT_en = 1'h1;
  assign crc_valid_d_crc_valid_MPORT_addr = d_source;
  assign crc_valid_d_crc_valid_MPORT_data = crc_valid[crc_valid_d_crc_valid_MPORT_addr]; // @[RAMModel.scala 163:26]
  assign crc_valid_MPORT_1_data = a_known_old & _a_crc_valid_T;
  assign crc_valid_MPORT_1_addr = a__source;
  assign crc_valid_MPORT_1_mask = 1'h1;
  assign crc_valid_MPORT_1_en = a_fire;
  assign auto_in_a_ready = auto_out_a_ready & ~wipe; // @[RAMModel.scala 51:33]
  assign auto_in_d_valid = auto_out_d_valid & _bundleIn_0_a_ready_T; // @[RAMModel.scala 55:33]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid & _bundleIn_0_a_ready_T; // @[RAMModel.scala 52:33]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = ~wipe; // @[RAMModel.scala 54:36]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready & ~wipe; // @[RAMModel.scala 51:33]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & _bundleIn_0_a_ready_T; // @[RAMModel.scala 55:33]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign alu_io_a_opcode = a__opcode; // @[RAMModel.scala 159:16]
  assign alu_io_a_mask = a__mask; // @[RAMModel.scala 159:16]
  assign alu_io_a_data = a__data; // @[RAMModel.scala 159:16]
  assign alu_io_data_in = {alu_io_data_in_hi,alu_io_data_in_lo}; // @[Cat.scala 33:92]
  always @(posedge clock) begin
    if (shadow_0_valid_MPORT_2_en & shadow_0_valid_MPORT_2_mask) begin
      shadow_0_valid[shadow_0_valid_MPORT_2_addr] <= shadow_0_valid_MPORT_2_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_0_value_MPORT_2_en & shadow_0_value_MPORT_2_mask) begin
      shadow_0_value[shadow_0_value_MPORT_2_addr] <= shadow_0_value_MPORT_2_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_1_valid_MPORT_3_en & shadow_1_valid_MPORT_3_mask) begin
      shadow_1_valid[shadow_1_valid_MPORT_3_addr] <= shadow_1_valid_MPORT_3_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_1_value_MPORT_3_en & shadow_1_value_MPORT_3_mask) begin
      shadow_1_value[shadow_1_value_MPORT_3_addr] <= shadow_1_value_MPORT_3_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_2_valid_MPORT_4_en & shadow_2_valid_MPORT_4_mask) begin
      shadow_2_valid[shadow_2_valid_MPORT_4_addr] <= shadow_2_valid_MPORT_4_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_2_value_MPORT_4_en & shadow_2_value_MPORT_4_mask) begin
      shadow_2_value[shadow_2_value_MPORT_4_addr] <= shadow_2_value_MPORT_4_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_3_valid_MPORT_5_en & shadow_3_valid_MPORT_5_mask) begin
      shadow_3_valid[shadow_3_valid_MPORT_5_addr] <= shadow_3_valid_MPORT_5_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_3_value_MPORT_5_en & shadow_3_value_MPORT_5_mask) begin
      shadow_3_value[shadow_3_value_MPORT_5_addr] <= shadow_3_value_MPORT_5_data; // @[RAMModel.scala 69:45]
    end
    if (inc_bytes_0_MPORT_6_en & inc_bytes_0_MPORT_6_mask) begin
      inc_bytes_0[inc_bytes_0_MPORT_6_addr] <= inc_bytes_0_MPORT_6_data; // @[RAMModel.scala 70:48]
    end
    if (inc_bytes_1_MPORT_7_en & inc_bytes_1_MPORT_7_mask) begin
      inc_bytes_1[inc_bytes_1_MPORT_7_addr] <= inc_bytes_1_MPORT_7_data; // @[RAMModel.scala 70:48]
    end
    if (inc_bytes_2_MPORT_8_en & inc_bytes_2_MPORT_8_mask) begin
      inc_bytes_2[inc_bytes_2_MPORT_8_addr] <= inc_bytes_2_MPORT_8_data; // @[RAMModel.scala 70:48]
    end
    if (inc_bytes_3_MPORT_9_en & inc_bytes_3_MPORT_9_mask) begin
      inc_bytes_3[inc_bytes_3_MPORT_9_addr] <= inc_bytes_3_MPORT_9_data; // @[RAMModel.scala 70:48]
    end
    if (dec_bytes_0_MPORT_18_en & dec_bytes_0_MPORT_18_mask) begin
      dec_bytes_0[dec_bytes_0_MPORT_18_addr] <= dec_bytes_0_MPORT_18_data; // @[RAMModel.scala 71:48]
    end
    if (dec_bytes_1_MPORT_19_en & dec_bytes_1_MPORT_19_mask) begin
      dec_bytes_1[dec_bytes_1_MPORT_19_addr] <= dec_bytes_1_MPORT_19_data; // @[RAMModel.scala 71:48]
    end
    if (dec_bytes_2_MPORT_20_en & dec_bytes_2_MPORT_20_mask) begin
      dec_bytes_2[dec_bytes_2_MPORT_20_addr] <= dec_bytes_2_MPORT_20_data; // @[RAMModel.scala 71:48]
    end
    if (dec_bytes_3_MPORT_21_en & dec_bytes_3_MPORT_21_mask) begin
      dec_bytes_3[dec_bytes_3_MPORT_21_addr] <= dec_bytes_3_MPORT_21_data; // @[RAMModel.scala 71:48]
    end
    if (inc_trees_0_MPORT_10_en & inc_trees_0_MPORT_10_mask) begin
      inc_trees_0[inc_trees_0_MPORT_10_addr] <= inc_trees_0_MPORT_10_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_1_MPORT_11_en & inc_trees_1_MPORT_11_mask) begin
      inc_trees_1[inc_trees_1_MPORT_11_addr] <= inc_trees_1_MPORT_11_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_2_MPORT_12_en & inc_trees_2_MPORT_12_mask) begin
      inc_trees_2[inc_trees_2_MPORT_12_addr] <= inc_trees_2_MPORT_12_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_3_MPORT_13_en & inc_trees_3_MPORT_13_mask) begin
      inc_trees_3[inc_trees_3_MPORT_13_addr] <= inc_trees_3_MPORT_13_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_4_MPORT_14_en & inc_trees_4_MPORT_14_mask) begin
      inc_trees_4[inc_trees_4_MPORT_14_addr] <= inc_trees_4_MPORT_14_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_5_MPORT_15_en & inc_trees_5_MPORT_15_mask) begin
      inc_trees_5[inc_trees_5_MPORT_15_addr] <= inc_trees_5_MPORT_15_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_6_MPORT_16_en & inc_trees_6_MPORT_16_mask) begin
      inc_trees_6[inc_trees_6_MPORT_16_addr] <= inc_trees_6_MPORT_16_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_7_MPORT_17_en & inc_trees_7_MPORT_17_mask) begin
      inc_trees_7[inc_trees_7_MPORT_17_addr] <= inc_trees_7_MPORT_17_data; // @[RAMModel.scala 72:56]
    end
    if (dec_trees_0_MPORT_22_en & dec_trees_0_MPORT_22_mask) begin
      dec_trees_0[dec_trees_0_MPORT_22_addr] <= dec_trees_0_MPORT_22_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_1_MPORT_23_en & dec_trees_1_MPORT_23_mask) begin
      dec_trees_1[dec_trees_1_MPORT_23_addr] <= dec_trees_1_MPORT_23_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_2_MPORT_24_en & dec_trees_2_MPORT_24_mask) begin
      dec_trees_2[dec_trees_2_MPORT_24_addr] <= dec_trees_2_MPORT_24_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_3_MPORT_25_en & dec_trees_3_MPORT_25_mask) begin
      dec_trees_3[dec_trees_3_MPORT_25_addr] <= dec_trees_3_MPORT_25_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_4_MPORT_26_en & dec_trees_4_MPORT_26_mask) begin
      dec_trees_4[dec_trees_4_MPORT_26_addr] <= dec_trees_4_MPORT_26_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_5_MPORT_27_en & dec_trees_5_MPORT_27_mask) begin
      dec_trees_5[dec_trees_5_MPORT_27_addr] <= dec_trees_5_MPORT_27_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_6_MPORT_28_en & dec_trees_6_MPORT_28_mask) begin
      dec_trees_6[dec_trees_6_MPORT_28_addr] <= dec_trees_6_MPORT_28_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_7_MPORT_29_en & dec_trees_7_MPORT_29_mask) begin
      dec_trees_7[dec_trees_7_MPORT_29_addr] <= dec_trees_7_MPORT_29_data; // @[RAMModel.scala 73:56]
    end
    if (crc_MPORT_en & crc_MPORT_mask) begin
      crc[crc_MPORT_addr] <= crc_MPORT_data; // @[RAMModel.scala 162:20]
    end
    if (crc_valid_MPORT_1_en & crc_valid_MPORT_1_mask) begin
      crc_valid[crc_valid_MPORT_1_addr] <= crc_valid_MPORT_1_data; // @[RAMModel.scala 163:26]
    end
    if (reset) begin // @[RAMModel.scala 46:30]
      wipeIndex <= 10'h0; // @[RAMModel.scala 46:30]
    end else begin
      wipeIndex <= _wipeIndex_T_1; // @[RAMModel.scala 48:17]
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h0 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_0_base <= auto_in_a_bits_address; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h0 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_0_size <= auto_in_a_bits_size; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h0 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_0_opcode <= auto_in_a_bits_opcode; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h1 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_1_base <= auto_in_a_bits_address; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h1 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_1_size <= auto_in_a_bits_size; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h1 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_1_opcode <= auto_in_a_bits_opcode; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h2 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_2_base <= auto_in_a_bits_address; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h2 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_2_size <= auto_in_a_bits_size; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h2 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_2_opcode <= auto_in_a_bits_opcode; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h3 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_3_base <= auto_in_a_bits_address; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h3 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_3_size <= auto_in_a_bits_size; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h3 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_3_opcode <= auto_in_a_bits_opcode; // @[RAMModel.scala 91:53]
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_flight_counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_d_flight_T_1) begin // @[Edges.scala 234:17]
      if (d_flight_first) begin // @[Edges.scala 235:21]
        if (d_flight_beats1_opdata) begin // @[Edges.scala 220:14]
          d_flight_counter <= d_flight_beats1_decode;
        end else begin
          d_flight_counter <= 8'h0;
        end
      end else begin
        d_flight_counter <= d_flight_counter1;
      end
    end
    if (d_flight_first) begin // @[Reg.scala 20:18]
      if (2'h3 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_base <= flight_3_base; // @[RAMModel.scala 93:35]
      end else if (2'h2 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_base <= flight_2_base; // @[RAMModel.scala 93:35]
      end else if (2'h1 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_base <= flight_1_base; // @[RAMModel.scala 93:35]
      end else begin
        d_flight_base <= flight_0_base;
      end
    end
    if (d_flight_first) begin // @[Reg.scala 20:18]
      if (2'h3 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_size <= flight_3_size; // @[RAMModel.scala 93:35]
      end else if (2'h2 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_size <= flight_2_size; // @[RAMModel.scala 93:35]
      end else if (2'h1 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_size <= flight_1_size; // @[RAMModel.scala 93:35]
      end else begin
        d_flight_size <= flight_0_size;
      end
    end
    if (d_flight_first) begin // @[Reg.scala 20:18]
      if (2'h3 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_opcode <= flight_3_opcode; // @[RAMModel.scala 93:35]
      end else if (2'h2 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_opcode <= flight_2_opcode; // @[RAMModel.scala 93:35]
      end else if (2'h1 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_opcode <= flight_1_opcode; // @[RAMModel.scala 93:35]
      end else begin
        d_flight_opcode <= flight_0_opcode;
      end
    end
    a__opcode <= auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__size <= auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__source <= auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__address <= auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__mask <= auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__data <= auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    if (reset) begin // @[RAMModel.scala 97:23]
      a_fire <= 1'h0; // @[RAMModel.scala 97:23]
    end else begin
      a_fire <= _T; // @[RAMModel.scala 97:23]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (a_fire) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 8'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    d_opcode <= auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    d_size <= auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    d_source <= auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    d_denied <= auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    d_data <= auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    if (reset) begin // @[RAMModel.scala 201:23]
      d_fire <= 1'h0; // @[RAMModel.scala 201:23]
    end else begin
      d_fire <= _d_flight_T_1; // @[RAMModel.scala 201:23]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (d_fire) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata_1) begin // @[Edges.scala 220:14]
          counter_1 <= beats1_decode_1;
        end else begin
          counter_1 <= 8'h0;
        end
      end else begin
        counter_1 <= counter1_1;
      end
    end
    if (d_fire) begin // @[RAMModel.scala 235:21]
      d_crc_reg <= d_crc; // @[RAMModel.scala 236:19]
    end
    if (d_first) begin // @[Reg.scala 20:18]
      d_crc_valid_r <= _d_crc_valid_T; // @[Reg.scala 20:22]
    end
    if (d_first) begin // @[Reg.scala 20:18]
      d_crc_check_r <= _d_crc_check_T; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & ~reset & ~(a__opcode != 3'h6 & a__opcode != 3'h7)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RAMModel.scala:119 assert (a.opcode =/= TLMessages.AcquireBlock && a.opcode =/= TLMessages.AcquirePerm)\n"
            ); // @[RAMModel.scala 119:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(a__opcode != 3'h6 & a__opcode != 3'h7) & (a_fire & ~reset)) begin
          $fatal; // @[RAMModel.scala 119:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_18 & a__mask[0] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 139:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_12 & _T_5) begin
          $fwrite(32'h80000002,"PF"); // @[RAMModel.scala 140:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_13 & _T_5) begin
          $fwrite(32'h80000002,"PP"); // @[RAMModel.scala 141:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_15 & _T_5) begin
          $fwrite(32'h80000002,"A "); // @[RAMModel.scala 142:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_17 & _T_5) begin
          $fwrite(32'h80000002,"L "); // @[RAMModel.scala 143:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x #%d %x\n",{a_addr_hi, 2'h0},byte_,busy,3'h0); // @[RAMModel.scala 144:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_18 & a__mask[1] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 139:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_12 & _T_5) begin
          $fwrite(32'h80000002,"PF"); // @[RAMModel.scala 140:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_13 & _T_5) begin
          $fwrite(32'h80000002,"PP"); // @[RAMModel.scala 141:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_15 & _T_5) begin
          $fwrite(32'h80000002,"A "); // @[RAMModel.scala 142:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_17 & _T_5) begin
          $fwrite(32'h80000002,"L "); // @[RAMModel.scala 143:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x #%d %x\n",_T_34 | 11'h1,byte_1,busy_1,3'h0); // @[RAMModel.scala 144:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_18 & a__mask[2] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 139:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_12 & _T_5) begin
          $fwrite(32'h80000002,"PF"); // @[RAMModel.scala 140:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_13 & _T_5) begin
          $fwrite(32'h80000002,"PP"); // @[RAMModel.scala 141:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_15 & _T_5) begin
          $fwrite(32'h80000002,"A "); // @[RAMModel.scala 142:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_17 & _T_5) begin
          $fwrite(32'h80000002,"L "); // @[RAMModel.scala 143:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x #%d %x\n",_T_34 | 11'h2,byte_2,busy_2,3'h0); // @[RAMModel.scala 144:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_18 & a__mask[3] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 139:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_12 & _T_5) begin
          $fwrite(32'h80000002,"PF"); // @[RAMModel.scala 140:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_13 & _T_5) begin
          $fwrite(32'h80000002,"PP"); // @[RAMModel.scala 141:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_15 & _T_5) begin
          $fwrite(32'h80000002,"A "); // @[RAMModel.scala 142:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_17 & _T_5) begin
          $fwrite(32'h80000002,"L "); // @[RAMModel.scala 143:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x #%d %x\n",_T_34 | 11'h3,byte_3,busy_3,3'h0); // @[RAMModel.scala 144:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_95 & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 G  0x%x - 0x%x\n",a__address,a__address | _T_99); // @[RAMModel.scala 150:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_5 & ~(d_size == d_flight_size)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:240 assert (d_size === d_flight.size)\n"); // @[RAMModel.scala 240:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_size == d_flight_size) & (d_fire & _T_5)) begin
          $fatal; // @[RAMModel.scala 240:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_147 & _T_5 & ~(d_opcode == 3'h2)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:244 assert (d.opcode === TLMessages.HintAck)\n"
            ); // @[RAMModel.scala 244:18]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_opcode == 3'h2) & (d_fire & _T_147 & _T_5)) begin
          $fatal; // @[RAMModel.scala 244:18]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_159 & _T_5 & ~(d_opcode == 3'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RAMModel.scala:266 assert (d.opcode === TLMessages.AccessAck)\n"); // @[RAMModel.scala 266:18]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_opcode == 3'h0) & (d_fire & _T_159 & _T_5)) begin
          $fatal; // @[RAMModel.scala 266:18]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_328 & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 267:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_328 & _T_157 & _T_5) begin
          $fwrite(32'h80000002,"pf"); // @[RAMModel.scala 268:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_328 & _T_158 & _T_5) begin
          $fwrite(32'h80000002,"pp"); // @[RAMModel.scala 269:72]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_328 & _T_5) begin
          $fwrite(32'h80000002," 0x%x - 0x%x\n",d_flight_base,d_flight_base | d_bits); // @[RAMModel.scala 270:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_183 & _T_5 & ~(d_opcode == 3'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RAMModel.scala:274 assert (d.opcode === TLMessages.AccessAckData)\n"); // @[RAMModel.scala 274:18]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_opcode == 3'h1) & (d_fire & _T_183 & _T_5)) begin
          $fatal; // @[RAMModel.scala 274:18]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_339 & d_mask[0] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 280:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_179 & _T_5) begin
          $fwrite(32'h80000002,"g "); // @[RAMModel.scala 281:65]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_180 & _T_5) begin
          $fwrite(32'h80000002,"a "); // @[RAMModel.scala 282:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_182 & _T_5) begin
          $fwrite(32'h80000002,"l "); // @[RAMModel.scala 283:73]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x",d_addr,got); // @[RAMModel.scala 284:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_202 & _T_5) begin
          $fwrite(32'h80000002,", undefined (uninitialized or prior overlapping puts)\n"); // @[RAMModel.scala 286:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & ~_T_202 & _T_205 & _T_5) begin
          $fwrite(32'h80000002,", undefined (concurrent incomplete puts #%d)\n",d_inc_0 - d_dec_0); // @[RAMModel.scala 288:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_363 & ~_T_205 & d_denied & _T_5) begin
          $fwrite(32'h80000002,", undefined (denied result)\n"); // @[RAMModel.scala 292:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_370 & _T_364 & _T_5) begin
          $fwrite(32'h80000002,"\n"); // @[RAMModel.scala 296:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_379 & shadow_value != got & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",shadow_value); // @[RAMModel.scala 297:53]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_379 & _T_5 & ~(shadow_value == got)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:298 assert (shadow.value === got)\n"); // @[RAMModel.scala 298:24]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(shadow_value == got) & (_GEN_379 & _T_5)) begin
          $fatal; // @[RAMModel.scala 298:24]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_339 & d_mask[1] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 280:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_179 & _T_5) begin
          $fwrite(32'h80000002,"g "); // @[RAMModel.scala 281:65]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_180 & _T_5) begin
          $fwrite(32'h80000002,"a "); // @[RAMModel.scala 282:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_182 & _T_5) begin
          $fwrite(32'h80000002,"l "); // @[RAMModel.scala 283:73]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x",d_addr_1,got_1); // @[RAMModel.scala 284:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_244 & _T_5) begin
          $fwrite(32'h80000002,", undefined (uninitialized or prior overlapping puts)\n"); // @[RAMModel.scala 286:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & ~_T_244 & _T_247 & _T_5) begin
          $fwrite(32'h80000002,", undefined (concurrent incomplete puts #%d)\n",d_inc_1 - d_dec_1); // @[RAMModel.scala 288:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_427 & ~_T_247 & d_denied & _T_5) begin
          $fwrite(32'h80000002,", undefined (denied result)\n"); // @[RAMModel.scala 292:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_434 & _T_364 & _T_5) begin
          $fwrite(32'h80000002,"\n"); // @[RAMModel.scala 296:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_443 & shadow_4_value != got_1 & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",shadow_4_value); // @[RAMModel.scala 297:53]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_443 & _T_5 & ~(shadow_4_value == got_1)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:298 assert (shadow.value === got)\n"); // @[RAMModel.scala 298:24]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(shadow_4_value == got_1) & (_GEN_443 & _T_5)) begin
          $fatal; // @[RAMModel.scala 298:24]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_339 & d_mask[2] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 280:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_179 & _T_5) begin
          $fwrite(32'h80000002,"g "); // @[RAMModel.scala 281:65]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_180 & _T_5) begin
          $fwrite(32'h80000002,"a "); // @[RAMModel.scala 282:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_182 & _T_5) begin
          $fwrite(32'h80000002,"l "); // @[RAMModel.scala 283:73]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x",d_addr_2,got_2); // @[RAMModel.scala 284:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_286 & _T_5) begin
          $fwrite(32'h80000002,", undefined (uninitialized or prior overlapping puts)\n"); // @[RAMModel.scala 286:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & ~_T_286 & _T_289 & _T_5) begin
          $fwrite(32'h80000002,", undefined (concurrent incomplete puts #%d)\n",d_inc_2 - d_dec_2); // @[RAMModel.scala 288:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_491 & ~_T_289 & d_denied & _T_5) begin
          $fwrite(32'h80000002,", undefined (denied result)\n"); // @[RAMModel.scala 292:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_498 & _T_364 & _T_5) begin
          $fwrite(32'h80000002,"\n"); // @[RAMModel.scala 296:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_507 & shadow_5_value != got_2 & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",shadow_5_value); // @[RAMModel.scala 297:53]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_507 & _T_5 & ~(shadow_5_value == got_2)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:298 assert (shadow.value === got)\n"); // @[RAMModel.scala 298:24]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(shadow_5_value == got_2) & (_GEN_507 & _T_5)) begin
          $fatal; // @[RAMModel.scala 298:24]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_339 & d_mask[3] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 "); // @[RAMModel.scala 280:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_179 & _T_5) begin
          $fwrite(32'h80000002,"g "); // @[RAMModel.scala 281:65]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_180 & _T_5) begin
          $fwrite(32'h80000002,"a "); // @[RAMModel.scala 282:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_182 & _T_5) begin
          $fwrite(32'h80000002,"l "); // @[RAMModel.scala 283:73]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x",d_addr_3,got_3); // @[RAMModel.scala 284:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_328 & _T_5) begin
          $fwrite(32'h80000002,", undefined (uninitialized or prior overlapping puts)\n"); // @[RAMModel.scala 286:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & ~_T_328 & _T_331 & _T_5) begin
          $fwrite(32'h80000002,", undefined (concurrent incomplete puts #%d)\n",d_inc_3 - d_dec_3); // @[RAMModel.scala 288:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_555 & ~_T_331 & d_denied & _T_5) begin
          $fwrite(32'h80000002,", undefined (denied result)\n"); // @[RAMModel.scala 292:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_562 & _T_364 & _T_5) begin
          $fwrite(32'h80000002,"\n"); // @[RAMModel.scala 296:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_571 & shadow_6_value != got_3 & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",shadow_6_value); // @[RAMModel.scala 297:53]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_571 & _T_5 & ~(shadow_6_value == got_3)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:298 assert (shadow.value === got)\n"); // @[RAMModel.scala 298:24]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(shadow_6_value == got_3) & (_GEN_571 & _T_5)) begin
          $fatal; // @[RAMModel.scala 298:24]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_358 & d_last & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 0 crc = 0x%x %d\n",d_crc,_GEN_152); // @[RAMModel.scala 311:19]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_601 & (~d_denied & _GEN_152 & d_crc != _GEN_153) & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",_GEN_153); // @[RAMModel.scala 312:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_601 & _T_5 & ~(d_denied | ~_GEN_152 | d_crc == _GEN_153)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RAMModel.scala:313 assert (corrupt || !must_match || d_crc === d_crc_check)\n"); // @[RAMModel.scala 313:20]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_denied | ~_GEN_152 | d_crc == _GEN_153) & (_GEN_601 & _T_5)) begin
          $fatal; // @[RAMModel.scala 313:20]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    shadow_0_valid[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    shadow_0_value[initvar] = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    shadow_1_valid[initvar] = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    shadow_1_value[initvar] = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    shadow_2_valid[initvar] = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    shadow_2_value[initvar] = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    shadow_3_valid[initvar] = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    shadow_3_value[initvar] = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    inc_bytes_0[initvar] = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    inc_bytes_1[initvar] = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    inc_bytes_2[initvar] = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    inc_bytes_3[initvar] = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    dec_bytes_0[initvar] = _RAND_12[1:0];
  _RAND_13 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    dec_bytes_1[initvar] = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    dec_bytes_2[initvar] = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    dec_bytes_3[initvar] = _RAND_15[1:0];
  _RAND_16 = {1{`RANDOM}};
  for (initvar = 0; initvar < 256; initvar = initvar+1)
    inc_trees_0[initvar] = _RAND_16[1:0];
  _RAND_17 = {1{`RANDOM}};
  for (initvar = 0; initvar < 128; initvar = initvar+1)
    inc_trees_1[initvar] = _RAND_17[1:0];
  _RAND_18 = {1{`RANDOM}};
  for (initvar = 0; initvar < 64; initvar = initvar+1)
    inc_trees_2[initvar] = _RAND_18[1:0];
  _RAND_19 = {1{`RANDOM}};
  for (initvar = 0; initvar < 32; initvar = initvar+1)
    inc_trees_3[initvar] = _RAND_19[1:0];
  _RAND_20 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    inc_trees_4[initvar] = _RAND_20[1:0];
  _RAND_21 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    inc_trees_5[initvar] = _RAND_21[1:0];
  _RAND_22 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    inc_trees_6[initvar] = _RAND_22[1:0];
  _RAND_23 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    inc_trees_7[initvar] = _RAND_23[1:0];
  _RAND_24 = {1{`RANDOM}};
  for (initvar = 0; initvar < 256; initvar = initvar+1)
    dec_trees_0[initvar] = _RAND_24[1:0];
  _RAND_25 = {1{`RANDOM}};
  for (initvar = 0; initvar < 128; initvar = initvar+1)
    dec_trees_1[initvar] = _RAND_25[1:0];
  _RAND_26 = {1{`RANDOM}};
  for (initvar = 0; initvar < 64; initvar = initvar+1)
    dec_trees_2[initvar] = _RAND_26[1:0];
  _RAND_27 = {1{`RANDOM}};
  for (initvar = 0; initvar < 32; initvar = initvar+1)
    dec_trees_3[initvar] = _RAND_27[1:0];
  _RAND_28 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    dec_trees_4[initvar] = _RAND_28[1:0];
  _RAND_29 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    dec_trees_5[initvar] = _RAND_29[1:0];
  _RAND_30 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    dec_trees_6[initvar] = _RAND_30[1:0];
  _RAND_31 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    dec_trees_7[initvar] = _RAND_31[1:0];
  _RAND_32 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    crc[initvar] = _RAND_32[15:0];
  _RAND_33 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    crc_valid[initvar] = _RAND_33[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_34 = {1{`RANDOM}};
  wipeIndex = _RAND_34[9:0];
  _RAND_35 = {1{`RANDOM}};
  flight_0_base = _RAND_35[10:0];
  _RAND_36 = {1{`RANDOM}};
  flight_0_size = _RAND_36[3:0];
  _RAND_37 = {1{`RANDOM}};
  flight_0_opcode = _RAND_37[2:0];
  _RAND_38 = {1{`RANDOM}};
  flight_1_base = _RAND_38[10:0];
  _RAND_39 = {1{`RANDOM}};
  flight_1_size = _RAND_39[3:0];
  _RAND_40 = {1{`RANDOM}};
  flight_1_opcode = _RAND_40[2:0];
  _RAND_41 = {1{`RANDOM}};
  flight_2_base = _RAND_41[10:0];
  _RAND_42 = {1{`RANDOM}};
  flight_2_size = _RAND_42[3:0];
  _RAND_43 = {1{`RANDOM}};
  flight_2_opcode = _RAND_43[2:0];
  _RAND_44 = {1{`RANDOM}};
  flight_3_base = _RAND_44[10:0];
  _RAND_45 = {1{`RANDOM}};
  flight_3_size = _RAND_45[3:0];
  _RAND_46 = {1{`RANDOM}};
  flight_3_opcode = _RAND_46[2:0];
  _RAND_47 = {1{`RANDOM}};
  d_flight_counter = _RAND_47[7:0];
  _RAND_48 = {1{`RANDOM}};
  d_flight_base = _RAND_48[10:0];
  _RAND_49 = {1{`RANDOM}};
  d_flight_size = _RAND_49[3:0];
  _RAND_50 = {1{`RANDOM}};
  d_flight_opcode = _RAND_50[2:0];
  _RAND_51 = {1{`RANDOM}};
  a__opcode = _RAND_51[2:0];
  _RAND_52 = {1{`RANDOM}};
  a__size = _RAND_52[3:0];
  _RAND_53 = {1{`RANDOM}};
  a__source = _RAND_53[1:0];
  _RAND_54 = {1{`RANDOM}};
  a__address = _RAND_54[10:0];
  _RAND_55 = {1{`RANDOM}};
  a__mask = _RAND_55[3:0];
  _RAND_56 = {1{`RANDOM}};
  a__data = _RAND_56[31:0];
  _RAND_57 = {1{`RANDOM}};
  a_fire = _RAND_57[0:0];
  _RAND_58 = {1{`RANDOM}};
  counter = _RAND_58[7:0];
  _RAND_59 = {1{`RANDOM}};
  d_opcode = _RAND_59[2:0];
  _RAND_60 = {1{`RANDOM}};
  d_size = _RAND_60[3:0];
  _RAND_61 = {1{`RANDOM}};
  d_source = _RAND_61[1:0];
  _RAND_62 = {1{`RANDOM}};
  d_denied = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  d_data = _RAND_63[31:0];
  _RAND_64 = {1{`RANDOM}};
  d_fire = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  counter_1 = _RAND_65[7:0];
  _RAND_66 = {1{`RANDOM}};
  d_crc_reg = _RAND_66[15:0];
  _RAND_67 = {1{`RANDOM}};
  d_crc_valid_r = _RAND_67[0:0];
  _RAND_68 = {1{`RANDOM}};
  d_crc_check_r = _RAND_68[15:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFilter_1(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [11:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [11:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_3(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [11:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [24:0] _is_aligned_mask_T_1 = 25'h3ff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [9:0] is_aligned_mask = ~_is_aligned_mask_T_1[9:0]; // @[package.scala 234:46]
  wire [11:0] _GEN_62 = {{2'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [11:0] _is_aligned_T = io_in_a_bits_address & _GEN_62; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 33:92]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_22 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire [11:0] _T_33 = io_in_a_bits_address ^ 12'h800; // @[Parameters.scala 137:31]
  wire [12:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [12:0] _T_36 = $signed(_T_34) & -13'sh800; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 13'sh0; // @[Parameters.scala 137:67]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 4'ha; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _T_22 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_413 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_417 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_469 = _T_417 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 52:35]
  wire [7:0] a_first_beats1_decode = is_aligned_mask[9:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [7:0] a_first_counter; // @[Edges.scala 228:27]
  wire [7:0] a_first_counter1 = a_first_counter - 8'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 8'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [11:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire [24:0] _d_first_beats1_decode_T_1 = 25'h3ff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [9:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [7:0] d_first_counter; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1 = d_first_counter - 8'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 8'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_588 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [3:0] inflight; // @[Monitor.scala 611:27]
  reg [15:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [31:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [7:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [7:0] a_first_counter1_1 = a_first_counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala 230:25]
  reg [7:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1_1 = d_first_counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_64 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_64}; // @[Monitor.scala 634:69]
  wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [31:0] _GEN_71 = {{16'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [31:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_71; // @[Monitor.scala 638:91]
  wire [31:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_597 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_73 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_73}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_328 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_328 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_329 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_329 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [3:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [3:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_330 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_330 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_331 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_331 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [46:0] _GEN_23 = _T_608 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _T_608 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [3:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_75 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [3:0] _inflight_T_1 = ~d_clr_wo_ready; // @[Monitor.scala 702:38]
  wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [15:0] a_opcodes_set = _GEN_19[15:0];
  wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [15:0] d_opcodes_clr = _GEN_23[15:0];
  wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [31:0] a_sizes_set = _GEN_20[31:0];
  wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [31:0] d_sizes_clr = _GEN_24[31:0];
  wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_1; // @[Monitor.scala 723:35]
  reg [31:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [7:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [7:0] d_first_counter1_2 = d_first_counter_2 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala 230:25]
  wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [31:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_71; // @[Monitor.scala 747:93]
  wire [31:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala 747:146]
  wire  _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [3:0] d_clr_wo_ready_1 = io_in_d_valid & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 779:89 780:22]
  wire [46:0] _GEN_69 = _T_696 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [3:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_714 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] _inflight_T_4 = ~d_clr_wo_ready_1; // @[Monitor.scala 809:46]
  wire [3:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [31:0] d_sizes_clr_1 = _GEN_69[31:0];
  wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [31:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 8'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 8'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 4'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 16'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 32'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 8'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 8'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | io_in_d_valid) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 4'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 32'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 8'h0; // @[Edges.scala 228:27]
    end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 8'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (io_in_d_valid) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_22) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_22 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_469 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_T_469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_469 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_588 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~io_in_a_ready) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~io_in_a_ready & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_704[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_704[0] & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_714) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Xbar.scala:313:5)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_714 & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_739) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Xbar.scala:313:5)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_739 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  size = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  source = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  address = _RAND_4[11:0];
  _RAND_5 = {1{`RANDOM}};
  d_first_counter = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  opcode_1 = _RAND_6[2:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[3:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  denied = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[3:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[15:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[7:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[7:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Atomics_1(
  input  [2:0]  io_a_opcode,
  input  [3:0]  io_a_mask,
  input  [31:0] io_a_data,
  input  [31:0] io_data_in,
  output [31:0] io_data_out
);
  wire [3:0] _signBit_T = ~io_a_mask; // @[Atomics.scala 23:42]
  wire [3:0] _signBit_T_2 = {1'h1,_signBit_T[3:1]}; // @[Cat.scala 33:92]
  wire [3:0] signBit = io_a_mask & _signBit_T_2; // @[Atomics.scala 23:27]
  wire [31:0] inv_d = ~io_data_in; // @[Atomics.scala 24:38]
  wire [7:0] _sum_T_5 = io_a_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_7 = io_a_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_9 = io_a_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _sum_T_11 = io_a_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [31:0] _sum_T_12 = {_sum_T_11,_sum_T_9,_sum_T_7,_sum_T_5}; // @[Cat.scala 33:92]
  wire [31:0] _sum_T_13 = _sum_T_12 & io_a_data; // @[Atomics.scala 25:44]
  wire [31:0] sum = _sum_T_13 + inv_d; // @[Atomics.scala 25:57]
  wire [3:0] _sign_a_T_32 = {io_a_data[31],io_a_data[23],io_a_data[15],io_a_data[7]}; // @[Cat.scala 33:92]
  wire [3:0] _sign_a_T_33 = _sign_a_T_32 & signBit; // @[Atomics.scala 26:83]
  wire  sign_a = |_sign_a_T_33; // @[Atomics.scala 26:97]
  wire [3:0] _sign_d_T_32 = {io_data_in[31],io_data_in[23],io_data_in[15],io_data_in[7]}; // @[Cat.scala 33:92]
  wire [3:0] _sign_d_T_33 = _sign_d_T_32 & signBit; // @[Atomics.scala 26:83]
  wire  sign_d = |_sign_d_T_33; // @[Atomics.scala 26:97]
  wire [3:0] _sign_s_T_32 = {sum[31],sum[23],sum[15],sum[7]}; // @[Cat.scala 33:92]
  wire [3:0] _sign_s_T_33 = _sign_s_T_32 & signBit; // @[Atomics.scala 26:83]
  wire  sign_s = |_sign_s_T_33; // @[Atomics.scala 26:97]
  wire  a_bigger_uneq = ~sign_a; // @[Atomics.scala 30:32]
  wire  a_bigger = sign_a == sign_d ? ~sign_s : a_bigger_uneq; // @[Atomics.scala 31:21]
  wire  pick_a = ~a_bigger; // @[Atomics.scala 32:25]
  wire [1:0] _logical_T_64 = {io_a_data[0],io_data_in[0]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_65 = 4'h6 >> _logical_T_64; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_67 = {io_a_data[1],io_data_in[1]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_68 = 4'h6 >> _logical_T_67; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_70 = {io_a_data[2],io_data_in[2]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_71 = 4'h6 >> _logical_T_70; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_73 = {io_a_data[3],io_data_in[3]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_74 = 4'h6 >> _logical_T_73; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_76 = {io_a_data[4],io_data_in[4]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_77 = 4'h6 >> _logical_T_76; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_79 = {io_a_data[5],io_data_in[5]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_80 = 4'h6 >> _logical_T_79; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_82 = {io_a_data[6],io_data_in[6]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_83 = 4'h6 >> _logical_T_82; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_85 = {io_a_data[7],io_data_in[7]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_86 = 4'h6 >> _logical_T_85; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_88 = {io_a_data[8],io_data_in[8]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_89 = 4'h6 >> _logical_T_88; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_91 = {io_a_data[9],io_data_in[9]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_92 = 4'h6 >> _logical_T_91; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_94 = {io_a_data[10],io_data_in[10]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_95 = 4'h6 >> _logical_T_94; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_97 = {io_a_data[11],io_data_in[11]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_98 = 4'h6 >> _logical_T_97; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_100 = {io_a_data[12],io_data_in[12]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_101 = 4'h6 >> _logical_T_100; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_103 = {io_a_data[13],io_data_in[13]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_104 = 4'h6 >> _logical_T_103; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_106 = {io_a_data[14],io_data_in[14]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_107 = 4'h6 >> _logical_T_106; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_109 = {io_a_data[15],io_data_in[15]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_110 = 4'h6 >> _logical_T_109; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_112 = {io_a_data[16],io_data_in[16]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_113 = 4'h6 >> _logical_T_112; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_115 = {io_a_data[17],io_data_in[17]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_116 = 4'h6 >> _logical_T_115; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_118 = {io_a_data[18],io_data_in[18]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_119 = 4'h6 >> _logical_T_118; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_121 = {io_a_data[19],io_data_in[19]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_122 = 4'h6 >> _logical_T_121; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_124 = {io_a_data[20],io_data_in[20]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_125 = 4'h6 >> _logical_T_124; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_127 = {io_a_data[21],io_data_in[21]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_128 = 4'h6 >> _logical_T_127; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_130 = {io_a_data[22],io_data_in[22]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_131 = 4'h6 >> _logical_T_130; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_133 = {io_a_data[23],io_data_in[23]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_134 = 4'h6 >> _logical_T_133; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_136 = {io_a_data[24],io_data_in[24]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_137 = 4'h6 >> _logical_T_136; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_139 = {io_a_data[25],io_data_in[25]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_140 = 4'h6 >> _logical_T_139; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_142 = {io_a_data[26],io_data_in[26]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_143 = 4'h6 >> _logical_T_142; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_145 = {io_a_data[27],io_data_in[27]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_146 = 4'h6 >> _logical_T_145; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_148 = {io_a_data[28],io_data_in[28]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_149 = 4'h6 >> _logical_T_148; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_151 = {io_a_data[29],io_data_in[29]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_152 = 4'h6 >> _logical_T_151; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_154 = {io_a_data[30],io_data_in[30]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_155 = 4'h6 >> _logical_T_154; // @[Atomics.scala 42:8]
  wire [1:0] _logical_T_157 = {io_a_data[31],io_data_in[31]}; // @[Cat.scala 33:92]
  wire [3:0] _logical_T_158 = 4'h6 >> _logical_T_157; // @[Atomics.scala 42:8]
  wire [7:0] logical_lo_lo = {_logical_T_86[0],_logical_T_83[0],_logical_T_80[0],_logical_T_77[0],_logical_T_74[0],
    _logical_T_71[0],_logical_T_68[0],_logical_T_65[0]}; // @[Cat.scala 33:92]
  wire [15:0] logical_lo = {_logical_T_110[0],_logical_T_107[0],_logical_T_104[0],_logical_T_101[0],_logical_T_98[0],
    _logical_T_95[0],_logical_T_92[0],_logical_T_89[0],logical_lo_lo}; // @[Cat.scala 33:92]
  wire [7:0] logical_hi_lo = {_logical_T_134[0],_logical_T_131[0],_logical_T_128[0],_logical_T_125[0],_logical_T_122[0],
    _logical_T_119[0],_logical_T_116[0],_logical_T_113[0]}; // @[Cat.scala 33:92]
  wire [31:0] logical = {_logical_T_158[0],_logical_T_155[0],_logical_T_152[0],_logical_T_149[0],_logical_T_146[0],
    _logical_T_143[0],_logical_T_140[0],_logical_T_137[0],logical_hi_lo,logical_lo}; // @[Cat.scala 33:92]
  wire [1:0] _select_T_1 = {{1'd0}, pick_a}; // @[Atomics.scala 49:8]
  wire [1:0] _GEN_6 = 3'h2 == io_a_opcode ? _select_T_1 : 2'h1; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_7 = 3'h3 == io_a_opcode ? 2'h3 : _GEN_6; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_8 = 3'h4 == io_a_opcode ? 2'h0 : _GEN_7; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_9 = 3'h5 == io_a_opcode ? 2'h0 : _GEN_8; // @[Atomics.scala 46:{19,19}]
  wire [1:0] _GEN_10 = 3'h6 == io_a_opcode ? 2'h0 : _GEN_9; // @[Atomics.scala 46:{19,19}]
  wire [1:0] select = 3'h7 == io_a_opcode ? 2'h0 : _GEN_10; // @[Atomics.scala 46:{19,19}]
  wire [1:0] selects_0 = io_a_mask[0] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_1 = io_a_mask[1] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_2 = io_a_mask[2] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [1:0] selects_3 = io_a_mask[3] ? select : 2'h0; // @[Atomics.scala 58:47]
  wire [7:0] _GEN_13 = 2'h1 == selects_1 ? io_a_data[15:8] : io_data_in[15:8]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_14 = 2'h2 == selects_1 ? sum[15:8] : _GEN_13; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_15 = 2'h3 == selects_1 ? logical[15:8] : _GEN_14; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_17 = 2'h1 == selects_0 ? io_a_data[7:0] : io_data_in[7:0]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_18 = 2'h2 == selects_0 ? sum[7:0] : _GEN_17; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_19 = 2'h3 == selects_0 ? logical[7:0] : _GEN_18; // @[Cat.scala 33:{92,92}]
  wire [15:0] io_data_out_lo = {_GEN_15,_GEN_19}; // @[Cat.scala 33:92]
  wire [7:0] _GEN_21 = 2'h1 == selects_3 ? io_a_data[31:24] : io_data_in[31:24]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_22 = 2'h2 == selects_3 ? sum[31:24] : _GEN_21; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_23 = 2'h3 == selects_3 ? logical[31:24] : _GEN_22; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_25 = 2'h1 == selects_2 ? io_a_data[23:16] : io_data_in[23:16]; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_26 = 2'h2 == selects_2 ? sum[23:16] : _GEN_25; // @[Cat.scala 33:{92,92}]
  wire [7:0] _GEN_27 = 2'h3 == selects_2 ? logical[23:16] : _GEN_26; // @[Cat.scala 33:{92,92}]
  wire [15:0] io_data_out_hi = {_GEN_23,_GEN_27}; // @[Cat.scala 33:92]
  assign io_data_out = {io_data_out_hi,io_data_out_lo}; // @[Cat.scala 33:92]
endmodule
module TLRAMModel_1(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [11:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [11:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [11:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  reg  shadow_0_valid [0:1023]; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_a_shadow_0_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_0_valid_a_shadow_0_addr; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_a_shadow_0_data; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_d_shadow_0_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_0_valid_d_shadow_0_addr; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_d_shadow_0_data; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_MPORT_2_data; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_0_valid_MPORT_2_addr; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_MPORT_2_mask; // @[RAMModel.scala 69:45]
  wire  shadow_0_valid_MPORT_2_en; // @[RAMModel.scala 69:45]
  reg [7:0] shadow_0_value [0:1023]; // @[RAMModel.scala 69:45]
  wire  shadow_0_value_a_shadow_0_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_0_value_a_shadow_0_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_0_value_a_shadow_0_data; // @[RAMModel.scala 69:45]
  wire  shadow_0_value_d_shadow_0_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_0_value_d_shadow_0_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_0_value_d_shadow_0_data; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_0_value_MPORT_2_data; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_0_value_MPORT_2_addr; // @[RAMModel.scala 69:45]
  wire  shadow_0_value_MPORT_2_mask; // @[RAMModel.scala 69:45]
  wire  shadow_0_value_MPORT_2_en; // @[RAMModel.scala 69:45]
  reg  shadow_1_valid [0:1023]; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_a_shadow_1_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_1_valid_a_shadow_1_addr; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_a_shadow_1_data; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_d_shadow_1_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_1_valid_d_shadow_1_addr; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_d_shadow_1_data; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_MPORT_3_data; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_1_valid_MPORT_3_addr; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_MPORT_3_mask; // @[RAMModel.scala 69:45]
  wire  shadow_1_valid_MPORT_3_en; // @[RAMModel.scala 69:45]
  reg [7:0] shadow_1_value [0:1023]; // @[RAMModel.scala 69:45]
  wire  shadow_1_value_a_shadow_1_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_1_value_a_shadow_1_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_1_value_a_shadow_1_data; // @[RAMModel.scala 69:45]
  wire  shadow_1_value_d_shadow_1_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_1_value_d_shadow_1_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_1_value_d_shadow_1_data; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_1_value_MPORT_3_data; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_1_value_MPORT_3_addr; // @[RAMModel.scala 69:45]
  wire  shadow_1_value_MPORT_3_mask; // @[RAMModel.scala 69:45]
  wire  shadow_1_value_MPORT_3_en; // @[RAMModel.scala 69:45]
  reg  shadow_2_valid [0:1023]; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_a_shadow_2_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_2_valid_a_shadow_2_addr; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_a_shadow_2_data; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_d_shadow_2_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_2_valid_d_shadow_2_addr; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_d_shadow_2_data; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_MPORT_4_data; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_2_valid_MPORT_4_addr; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_MPORT_4_mask; // @[RAMModel.scala 69:45]
  wire  shadow_2_valid_MPORT_4_en; // @[RAMModel.scala 69:45]
  reg [7:0] shadow_2_value [0:1023]; // @[RAMModel.scala 69:45]
  wire  shadow_2_value_a_shadow_2_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_2_value_a_shadow_2_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_2_value_a_shadow_2_data; // @[RAMModel.scala 69:45]
  wire  shadow_2_value_d_shadow_2_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_2_value_d_shadow_2_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_2_value_d_shadow_2_data; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_2_value_MPORT_4_data; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_2_value_MPORT_4_addr; // @[RAMModel.scala 69:45]
  wire  shadow_2_value_MPORT_4_mask; // @[RAMModel.scala 69:45]
  wire  shadow_2_value_MPORT_4_en; // @[RAMModel.scala 69:45]
  reg  shadow_3_valid [0:1023]; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_a_shadow_3_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_3_valid_a_shadow_3_addr; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_a_shadow_3_data; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_d_shadow_3_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_3_valid_d_shadow_3_addr; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_d_shadow_3_data; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_MPORT_5_data; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_3_valid_MPORT_5_addr; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_MPORT_5_mask; // @[RAMModel.scala 69:45]
  wire  shadow_3_valid_MPORT_5_en; // @[RAMModel.scala 69:45]
  reg [7:0] shadow_3_value [0:1023]; // @[RAMModel.scala 69:45]
  wire  shadow_3_value_a_shadow_3_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_3_value_a_shadow_3_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_3_value_a_shadow_3_data; // @[RAMModel.scala 69:45]
  wire  shadow_3_value_d_shadow_3_en; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_3_value_d_shadow_3_addr; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_3_value_d_shadow_3_data; // @[RAMModel.scala 69:45]
  wire [7:0] shadow_3_value_MPORT_5_data; // @[RAMModel.scala 69:45]
  wire [9:0] shadow_3_value_MPORT_5_addr; // @[RAMModel.scala 69:45]
  wire  shadow_3_value_MPORT_5_mask; // @[RAMModel.scala 69:45]
  wire  shadow_3_value_MPORT_5_en; // @[RAMModel.scala 69:45]
  reg [1:0] inc_bytes_0 [0:1023]; // @[RAMModel.scala 70:48]
  wire  inc_bytes_0_a_inc_bytes_0_en; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_0_a_inc_bytes_0_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_0_a_inc_bytes_0_data; // @[RAMModel.scala 70:48]
  wire  inc_bytes_0_d_inc_bytes_0_en; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_0_d_inc_bytes_0_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_0_d_inc_bytes_0_data; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_0_MPORT_6_data; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_0_MPORT_6_addr; // @[RAMModel.scala 70:48]
  wire  inc_bytes_0_MPORT_6_mask; // @[RAMModel.scala 70:48]
  wire  inc_bytes_0_MPORT_6_en; // @[RAMModel.scala 70:48]
  reg [1:0] inc_bytes_1 [0:1023]; // @[RAMModel.scala 70:48]
  wire  inc_bytes_1_a_inc_bytes_1_en; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_1_a_inc_bytes_1_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_1_a_inc_bytes_1_data; // @[RAMModel.scala 70:48]
  wire  inc_bytes_1_d_inc_bytes_1_en; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_1_d_inc_bytes_1_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_1_d_inc_bytes_1_data; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_1_MPORT_7_data; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_1_MPORT_7_addr; // @[RAMModel.scala 70:48]
  wire  inc_bytes_1_MPORT_7_mask; // @[RAMModel.scala 70:48]
  wire  inc_bytes_1_MPORT_7_en; // @[RAMModel.scala 70:48]
  reg [1:0] inc_bytes_2 [0:1023]; // @[RAMModel.scala 70:48]
  wire  inc_bytes_2_a_inc_bytes_2_en; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_2_a_inc_bytes_2_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_2_a_inc_bytes_2_data; // @[RAMModel.scala 70:48]
  wire  inc_bytes_2_d_inc_bytes_2_en; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_2_d_inc_bytes_2_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_2_d_inc_bytes_2_data; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_2_MPORT_8_data; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_2_MPORT_8_addr; // @[RAMModel.scala 70:48]
  wire  inc_bytes_2_MPORT_8_mask; // @[RAMModel.scala 70:48]
  wire  inc_bytes_2_MPORT_8_en; // @[RAMModel.scala 70:48]
  reg [1:0] inc_bytes_3 [0:1023]; // @[RAMModel.scala 70:48]
  wire  inc_bytes_3_a_inc_bytes_3_en; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_3_a_inc_bytes_3_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_3_a_inc_bytes_3_data; // @[RAMModel.scala 70:48]
  wire  inc_bytes_3_d_inc_bytes_3_en; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_3_d_inc_bytes_3_addr; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_3_d_inc_bytes_3_data; // @[RAMModel.scala 70:48]
  wire [1:0] inc_bytes_3_MPORT_9_data; // @[RAMModel.scala 70:48]
  wire [9:0] inc_bytes_3_MPORT_9_addr; // @[RAMModel.scala 70:48]
  wire  inc_bytes_3_MPORT_9_mask; // @[RAMModel.scala 70:48]
  wire  inc_bytes_3_MPORT_9_en; // @[RAMModel.scala 70:48]
  reg [1:0] dec_bytes_0 [0:1023]; // @[RAMModel.scala 71:48]
  wire  dec_bytes_0_a_dec_bytes_0_en; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_0_a_dec_bytes_0_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_0_a_dec_bytes_0_data; // @[RAMModel.scala 71:48]
  wire  dec_bytes_0_d_dec_bytes_0_en; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_0_d_dec_bytes_0_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_0_d_dec_bytes_0_data; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_0_MPORT_18_data; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_0_MPORT_18_addr; // @[RAMModel.scala 71:48]
  wire  dec_bytes_0_MPORT_18_mask; // @[RAMModel.scala 71:48]
  wire  dec_bytes_0_MPORT_18_en; // @[RAMModel.scala 71:48]
  reg [1:0] dec_bytes_1 [0:1023]; // @[RAMModel.scala 71:48]
  wire  dec_bytes_1_a_dec_bytes_1_en; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_1_a_dec_bytes_1_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_1_a_dec_bytes_1_data; // @[RAMModel.scala 71:48]
  wire  dec_bytes_1_d_dec_bytes_1_en; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_1_d_dec_bytes_1_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_1_d_dec_bytes_1_data; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_1_MPORT_19_data; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_1_MPORT_19_addr; // @[RAMModel.scala 71:48]
  wire  dec_bytes_1_MPORT_19_mask; // @[RAMModel.scala 71:48]
  wire  dec_bytes_1_MPORT_19_en; // @[RAMModel.scala 71:48]
  reg [1:0] dec_bytes_2 [0:1023]; // @[RAMModel.scala 71:48]
  wire  dec_bytes_2_a_dec_bytes_2_en; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_2_a_dec_bytes_2_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_2_a_dec_bytes_2_data; // @[RAMModel.scala 71:48]
  wire  dec_bytes_2_d_dec_bytes_2_en; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_2_d_dec_bytes_2_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_2_d_dec_bytes_2_data; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_2_MPORT_20_data; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_2_MPORT_20_addr; // @[RAMModel.scala 71:48]
  wire  dec_bytes_2_MPORT_20_mask; // @[RAMModel.scala 71:48]
  wire  dec_bytes_2_MPORT_20_en; // @[RAMModel.scala 71:48]
  reg [1:0] dec_bytes_3 [0:1023]; // @[RAMModel.scala 71:48]
  wire  dec_bytes_3_a_dec_bytes_3_en; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_3_a_dec_bytes_3_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_3_a_dec_bytes_3_data; // @[RAMModel.scala 71:48]
  wire  dec_bytes_3_d_dec_bytes_3_en; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_3_d_dec_bytes_3_addr; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_3_d_dec_bytes_3_data; // @[RAMModel.scala 71:48]
  wire [1:0] dec_bytes_3_MPORT_21_data; // @[RAMModel.scala 71:48]
  wire [9:0] dec_bytes_3_MPORT_21_addr; // @[RAMModel.scala 71:48]
  wire  dec_bytes_3_MPORT_21_mask; // @[RAMModel.scala 71:48]
  wire  dec_bytes_3_MPORT_21_en; // @[RAMModel.scala 71:48]
  reg [1:0] inc_trees_0 [0:511]; // @[RAMModel.scala 72:56]
  wire  inc_trees_0_a_inc_trees_0_en; // @[RAMModel.scala 72:56]
  wire [8:0] inc_trees_0_a_inc_trees_0_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_0_a_inc_trees_0_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_0_d_inc_trees_0_en; // @[RAMModel.scala 72:56]
  wire [8:0] inc_trees_0_d_inc_trees_0_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_0_d_inc_trees_0_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_0_MPORT_10_data; // @[RAMModel.scala 72:56]
  wire [8:0] inc_trees_0_MPORT_10_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_0_MPORT_10_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_0_MPORT_10_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_1 [0:255]; // @[RAMModel.scala 72:56]
  wire  inc_trees_1_a_inc_trees_1_en; // @[RAMModel.scala 72:56]
  wire [7:0] inc_trees_1_a_inc_trees_1_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_1_a_inc_trees_1_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_1_d_inc_trees_1_en; // @[RAMModel.scala 72:56]
  wire [7:0] inc_trees_1_d_inc_trees_1_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_1_d_inc_trees_1_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_1_MPORT_11_data; // @[RAMModel.scala 72:56]
  wire [7:0] inc_trees_1_MPORT_11_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_1_MPORT_11_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_1_MPORT_11_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_2 [0:127]; // @[RAMModel.scala 72:56]
  wire  inc_trees_2_a_inc_trees_2_en; // @[RAMModel.scala 72:56]
  wire [6:0] inc_trees_2_a_inc_trees_2_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_2_a_inc_trees_2_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_2_d_inc_trees_2_en; // @[RAMModel.scala 72:56]
  wire [6:0] inc_trees_2_d_inc_trees_2_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_2_d_inc_trees_2_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_2_MPORT_12_data; // @[RAMModel.scala 72:56]
  wire [6:0] inc_trees_2_MPORT_12_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_2_MPORT_12_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_2_MPORT_12_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_3 [0:63]; // @[RAMModel.scala 72:56]
  wire  inc_trees_3_a_inc_trees_3_en; // @[RAMModel.scala 72:56]
  wire [5:0] inc_trees_3_a_inc_trees_3_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_3_a_inc_trees_3_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_3_d_inc_trees_3_en; // @[RAMModel.scala 72:56]
  wire [5:0] inc_trees_3_d_inc_trees_3_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_3_d_inc_trees_3_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_3_MPORT_13_data; // @[RAMModel.scala 72:56]
  wire [5:0] inc_trees_3_MPORT_13_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_3_MPORT_13_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_3_MPORT_13_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_4 [0:31]; // @[RAMModel.scala 72:56]
  wire  inc_trees_4_a_inc_trees_4_en; // @[RAMModel.scala 72:56]
  wire [4:0] inc_trees_4_a_inc_trees_4_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_4_a_inc_trees_4_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_4_d_inc_trees_4_en; // @[RAMModel.scala 72:56]
  wire [4:0] inc_trees_4_d_inc_trees_4_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_4_d_inc_trees_4_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_4_MPORT_14_data; // @[RAMModel.scala 72:56]
  wire [4:0] inc_trees_4_MPORT_14_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_4_MPORT_14_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_4_MPORT_14_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_5 [0:15]; // @[RAMModel.scala 72:56]
  wire  inc_trees_5_a_inc_trees_5_en; // @[RAMModel.scala 72:56]
  wire [3:0] inc_trees_5_a_inc_trees_5_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_5_a_inc_trees_5_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_5_d_inc_trees_5_en; // @[RAMModel.scala 72:56]
  wire [3:0] inc_trees_5_d_inc_trees_5_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_5_d_inc_trees_5_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_5_MPORT_15_data; // @[RAMModel.scala 72:56]
  wire [3:0] inc_trees_5_MPORT_15_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_5_MPORT_15_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_5_MPORT_15_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_6 [0:7]; // @[RAMModel.scala 72:56]
  wire  inc_trees_6_a_inc_trees_6_en; // @[RAMModel.scala 72:56]
  wire [2:0] inc_trees_6_a_inc_trees_6_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_a_inc_trees_6_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_6_d_inc_trees_6_en; // @[RAMModel.scala 72:56]
  wire [2:0] inc_trees_6_d_inc_trees_6_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_d_inc_trees_6_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_6_MPORT_16_data; // @[RAMModel.scala 72:56]
  wire [2:0] inc_trees_6_MPORT_16_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_6_MPORT_16_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_6_MPORT_16_en; // @[RAMModel.scala 72:56]
  reg [1:0] inc_trees_7 [0:3]; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_a_inc_trees_7_en; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_a_inc_trees_7_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_a_inc_trees_7_data; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_d_inc_trees_7_en; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_d_inc_trees_7_addr; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_d_inc_trees_7_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_MPORT_17_data; // @[RAMModel.scala 72:56]
  wire [1:0] inc_trees_7_MPORT_17_addr; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_MPORT_17_mask; // @[RAMModel.scala 72:56]
  wire  inc_trees_7_MPORT_17_en; // @[RAMModel.scala 72:56]
  reg [1:0] dec_trees_0 [0:511]; // @[RAMModel.scala 73:56]
  wire  dec_trees_0_a_dec_trees_0_en; // @[RAMModel.scala 73:56]
  wire [8:0] dec_trees_0_a_dec_trees_0_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_0_a_dec_trees_0_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_0_d_dec_trees_0_en; // @[RAMModel.scala 73:56]
  wire [8:0] dec_trees_0_d_dec_trees_0_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_0_d_dec_trees_0_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_0_MPORT_22_data; // @[RAMModel.scala 73:56]
  wire [8:0] dec_trees_0_MPORT_22_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_0_MPORT_22_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_0_MPORT_22_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_1 [0:255]; // @[RAMModel.scala 73:56]
  wire  dec_trees_1_a_dec_trees_1_en; // @[RAMModel.scala 73:56]
  wire [7:0] dec_trees_1_a_dec_trees_1_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_1_a_dec_trees_1_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_1_d_dec_trees_1_en; // @[RAMModel.scala 73:56]
  wire [7:0] dec_trees_1_d_dec_trees_1_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_1_d_dec_trees_1_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_1_MPORT_23_data; // @[RAMModel.scala 73:56]
  wire [7:0] dec_trees_1_MPORT_23_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_1_MPORT_23_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_1_MPORT_23_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_2 [0:127]; // @[RAMModel.scala 73:56]
  wire  dec_trees_2_a_dec_trees_2_en; // @[RAMModel.scala 73:56]
  wire [6:0] dec_trees_2_a_dec_trees_2_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_2_a_dec_trees_2_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_2_d_dec_trees_2_en; // @[RAMModel.scala 73:56]
  wire [6:0] dec_trees_2_d_dec_trees_2_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_2_d_dec_trees_2_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_2_MPORT_24_data; // @[RAMModel.scala 73:56]
  wire [6:0] dec_trees_2_MPORT_24_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_2_MPORT_24_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_2_MPORT_24_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_3 [0:63]; // @[RAMModel.scala 73:56]
  wire  dec_trees_3_a_dec_trees_3_en; // @[RAMModel.scala 73:56]
  wire [5:0] dec_trees_3_a_dec_trees_3_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_3_a_dec_trees_3_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_3_d_dec_trees_3_en; // @[RAMModel.scala 73:56]
  wire [5:0] dec_trees_3_d_dec_trees_3_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_3_d_dec_trees_3_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_3_MPORT_25_data; // @[RAMModel.scala 73:56]
  wire [5:0] dec_trees_3_MPORT_25_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_3_MPORT_25_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_3_MPORT_25_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_4 [0:31]; // @[RAMModel.scala 73:56]
  wire  dec_trees_4_a_dec_trees_4_en; // @[RAMModel.scala 73:56]
  wire [4:0] dec_trees_4_a_dec_trees_4_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_4_a_dec_trees_4_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_4_d_dec_trees_4_en; // @[RAMModel.scala 73:56]
  wire [4:0] dec_trees_4_d_dec_trees_4_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_4_d_dec_trees_4_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_4_MPORT_26_data; // @[RAMModel.scala 73:56]
  wire [4:0] dec_trees_4_MPORT_26_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_4_MPORT_26_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_4_MPORT_26_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_5 [0:15]; // @[RAMModel.scala 73:56]
  wire  dec_trees_5_a_dec_trees_5_en; // @[RAMModel.scala 73:56]
  wire [3:0] dec_trees_5_a_dec_trees_5_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_5_a_dec_trees_5_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_5_d_dec_trees_5_en; // @[RAMModel.scala 73:56]
  wire [3:0] dec_trees_5_d_dec_trees_5_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_5_d_dec_trees_5_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_5_MPORT_27_data; // @[RAMModel.scala 73:56]
  wire [3:0] dec_trees_5_MPORT_27_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_5_MPORT_27_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_5_MPORT_27_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_6 [0:7]; // @[RAMModel.scala 73:56]
  wire  dec_trees_6_a_dec_trees_6_en; // @[RAMModel.scala 73:56]
  wire [2:0] dec_trees_6_a_dec_trees_6_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_a_dec_trees_6_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_6_d_dec_trees_6_en; // @[RAMModel.scala 73:56]
  wire [2:0] dec_trees_6_d_dec_trees_6_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_d_dec_trees_6_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_6_MPORT_28_data; // @[RAMModel.scala 73:56]
  wire [2:0] dec_trees_6_MPORT_28_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_6_MPORT_28_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_6_MPORT_28_en; // @[RAMModel.scala 73:56]
  reg [1:0] dec_trees_7 [0:3]; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_a_dec_trees_7_en; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_a_dec_trees_7_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_a_dec_trees_7_data; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_d_dec_trees_7_en; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_d_dec_trees_7_addr; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_d_dec_trees_7_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_MPORT_29_data; // @[RAMModel.scala 73:56]
  wire [1:0] dec_trees_7_MPORT_29_addr; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_MPORT_29_mask; // @[RAMModel.scala 73:56]
  wire  dec_trees_7_MPORT_29_en; // @[RAMModel.scala 73:56]
  wire [2:0] alu_io_a_opcode; // @[RAMModel.scala 157:23]
  wire [3:0] alu_io_a_mask; // @[RAMModel.scala 157:23]
  wire [31:0] alu_io_a_data; // @[RAMModel.scala 157:23]
  wire [31:0] alu_io_data_in; // @[RAMModel.scala 157:23]
  wire [31:0] alu_io_data_out; // @[RAMModel.scala 157:23]
  reg [15:0] crc [0:3]; // @[RAMModel.scala 162:20]
  wire  crc_a_crc_acc_MPORT_en; // @[RAMModel.scala 162:20]
  wire [1:0] crc_a_crc_acc_MPORT_addr; // @[RAMModel.scala 162:20]
  wire [15:0] crc_a_crc_acc_MPORT_data; // @[RAMModel.scala 162:20]
  wire  crc_d_crc_check_MPORT_en; // @[RAMModel.scala 162:20]
  wire [1:0] crc_d_crc_check_MPORT_addr; // @[RAMModel.scala 162:20]
  wire [15:0] crc_d_crc_check_MPORT_data; // @[RAMModel.scala 162:20]
  wire [15:0] crc_MPORT_data; // @[RAMModel.scala 162:20]
  wire [1:0] crc_MPORT_addr; // @[RAMModel.scala 162:20]
  wire  crc_MPORT_mask; // @[RAMModel.scala 162:20]
  wire  crc_MPORT_en; // @[RAMModel.scala 162:20]
  reg  crc_valid [0:3]; // @[RAMModel.scala 163:26]
  wire  crc_valid_a_crc_valid_MPORT_en; // @[RAMModel.scala 163:26]
  wire [1:0] crc_valid_a_crc_valid_MPORT_addr; // @[RAMModel.scala 163:26]
  wire  crc_valid_a_crc_valid_MPORT_data; // @[RAMModel.scala 163:26]
  wire  crc_valid_d_crc_valid_MPORT_en; // @[RAMModel.scala 163:26]
  wire [1:0] crc_valid_d_crc_valid_MPORT_addr; // @[RAMModel.scala 163:26]
  wire  crc_valid_d_crc_valid_MPORT_data; // @[RAMModel.scala 163:26]
  wire  crc_valid_MPORT_1_data; // @[RAMModel.scala 163:26]
  wire [1:0] crc_valid_MPORT_1_addr; // @[RAMModel.scala 163:26]
  wire  crc_valid_MPORT_1_mask; // @[RAMModel.scala 163:26]
  wire  crc_valid_MPORT_1_en; // @[RAMModel.scala 163:26]
  reg [10:0] wipeIndex; // @[RAMModel.scala 46:30]
  wire  wipe = ~wipeIndex[10]; // @[RAMModel.scala 47:18]
  wire [10:0] _GEN_237 = {{10'd0}, wipe}; // @[RAMModel.scala 48:30]
  wire [10:0] _wipeIndex_T_1 = wipeIndex + _GEN_237; // @[RAMModel.scala 48:30]
  wire  _bundleIn_0_a_ready_T = ~wipe; // @[RAMModel.scala 51:36]
  wire  bundleIn_0_a_ready = auto_out_a_ready & ~wipe; // @[RAMModel.scala 51:33]
  wire [3:0] shadow_wen_x9 = wipe ? 4'hf : 4'h0; // @[Bitwise.scala 77:12]
  wire [7:0] inc_trees_wen_x15 = wipe ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  reg [11:0] flight_0_base; // @[RAMModel.scala 82:23]
  reg [3:0] flight_0_size; // @[RAMModel.scala 82:23]
  reg [2:0] flight_0_opcode; // @[RAMModel.scala 82:23]
  reg [11:0] flight_1_base; // @[RAMModel.scala 82:23]
  reg [3:0] flight_1_size; // @[RAMModel.scala 82:23]
  reg [2:0] flight_1_opcode; // @[RAMModel.scala 82:23]
  reg [11:0] flight_2_base; // @[RAMModel.scala 82:23]
  reg [3:0] flight_2_size; // @[RAMModel.scala 82:23]
  reg [2:0] flight_2_opcode; // @[RAMModel.scala 82:23]
  reg [11:0] flight_3_base; // @[RAMModel.scala 82:23]
  reg [3:0] flight_3_size; // @[RAMModel.scala 82:23]
  reg [2:0] flight_3_opcode; // @[RAMModel.scala 82:23]
  wire  _T = bundleIn_0_a_ready & auto_in_a_valid; // @[Decoupled.scala 52:35]
  wire  _d_flight_T_1 = _bundleIn_0_a_ready_T & auto_out_d_valid; // @[Decoupled.scala 52:35]
  wire [24:0] _d_flight_beats1_decode_T_1 = 25'h3ff << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [9:0] _d_flight_beats1_decode_T_3 = ~_d_flight_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] d_flight_beats1_decode = _d_flight_beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire  d_flight_beats1_opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [7:0] d_flight_counter; // @[Edges.scala 228:27]
  wire [7:0] d_flight_counter1 = d_flight_counter - 8'h1; // @[Edges.scala 229:28]
  wire  d_flight_first = d_flight_counter == 8'h0; // @[Edges.scala 230:25]
  reg [11:0] d_flight_base; // @[Reg.scala 19:16]
  reg [3:0] d_flight_size; // @[Reg.scala 19:16]
  reg [2:0] d_flight_opcode; // @[Reg.scala 19:16]
  reg [2:0] a__opcode; // @[RAMModel.scala 96:18]
  reg [3:0] a__size; // @[RAMModel.scala 96:18]
  reg [1:0] a__source; // @[RAMModel.scala 96:18]
  reg [11:0] a__address; // @[RAMModel.scala 96:18]
  reg [3:0] a__mask; // @[RAMModel.scala 96:18]
  reg [31:0] a__data; // @[RAMModel.scala 96:18]
  reg  a_fire; // @[RAMModel.scala 97:23]
  wire [24:0] _beats1_decode_T_1 = 25'h3ff << a__size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode = _beats1_decode_T_3[9:2]; // @[Edges.scala 219:59]
  wire  beats1_opdata = ~a__opcode[2]; // @[Edges.scala 91:28]
  wire [7:0] beats1 = beats1_opdata ? beats1_decode : 8'h0; // @[Edges.scala 220:14]
  reg [7:0] counter; // @[Edges.scala 228:27]
  wire [7:0] counter1 = counter - 8'h1; // @[Edges.scala 229:28]
  wire  a_first = counter == 8'h0; // @[Edges.scala 230:25]
  wire [7:0] _count_T = ~counter1; // @[Edges.scala 233:27]
  wire [7:0] count = beats1 & _count_T; // @[Edges.scala 233:25]
  wire [9:0] a_address_inc = {count, 2'h0}; // @[Edges.scala 268:29]
  wire [15:0] a_sizeOH = 16'h1 << a__size; // @[OneHot.scala 57:35]
  wire [11:0] _GEN_238 = {{2'd0}, a_address_inc}; // @[RAMModel.scala 101:33]
  wire [11:0] a_address = a__address | _GEN_238; // @[RAMModel.scala 101:33]
  wire [9:0] a_addr_hi = a_address[11:2]; // @[Edges.scala 191:34]
  wire  a_mask_sizeOH_shiftAmount = a__size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _a_mask_sizeOH_T_1 = 2'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] a_mask_sizeOH = _a_mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _a_mask_T = a__size >= 4'h2; // @[Misc.scala 205:21]
  wire  a_mask_size = a_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  a_mask_bit = a__address[1]; // @[Misc.scala 209:26]
  wire  a_mask_nbit = ~a_mask_bit; // @[Misc.scala 210:20]
  wire  a_mask_acc = _a_mask_T | a_mask_size & a_mask_nbit; // @[Misc.scala 214:29]
  wire  a_mask_acc_1 = _a_mask_T | a_mask_size & a_mask_bit; // @[Misc.scala 214:29]
  wire  a_mask_size_1 = a_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  a_mask_bit_1 = a__address[0]; // @[Misc.scala 209:26]
  wire  a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala 210:20]
  wire  a_mask_eq_2 = a_mask_nbit & a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_2 = a_mask_acc | a_mask_size_1 & a_mask_eq_2; // @[Misc.scala 214:29]
  wire  a_mask_eq_3 = a_mask_nbit & a_mask_bit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_3 = a_mask_acc | a_mask_size_1 & a_mask_eq_3; // @[Misc.scala 214:29]
  wire  a_mask_eq_4 = a_mask_bit & a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_4 = a_mask_acc_1 | a_mask_size_1 & a_mask_eq_4; // @[Misc.scala 214:29]
  wire  a_mask_eq_5 = a_mask_bit & a_mask_bit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_5 = a_mask_acc_1 | a_mask_size_1 & a_mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] a_mask = {a_mask_acc_5,a_mask_acc_4,a_mask_acc_3,a_mask_acc_2}; // @[Cat.scala 33:92]
  wire [2:0] _a_inc_tree_T = {{1'd0}, inc_trees_0_a_inc_trees_0_data}; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_3 = _a_inc_tree_T[1:0] + inc_trees_1_a_inc_trees_1_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_5 = _a_inc_tree_T_3 + inc_trees_2_a_inc_trees_2_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_7 = _a_inc_tree_T_5 + inc_trees_3_a_inc_trees_3_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_9 = _a_inc_tree_T_7 + inc_trees_4_a_inc_trees_4_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_11 = _a_inc_tree_T_9 + inc_trees_5_a_inc_trees_5_data; // @[RAMModel.scala 112:52]
  wire [1:0] _a_inc_tree_T_13 = _a_inc_tree_T_11 + inc_trees_6_a_inc_trees_6_data; // @[RAMModel.scala 112:52]
  wire [1:0] a_inc_tree = _a_inc_tree_T_13 + inc_trees_7_a_inc_trees_7_data; // @[RAMModel.scala 112:52]
  wire [2:0] _a_dec_tree_T = {{1'd0}, dec_trees_0_a_dec_trees_0_data}; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_3 = _a_dec_tree_T[1:0] + dec_trees_1_a_dec_trees_1_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_5 = _a_dec_tree_T_3 + dec_trees_2_a_dec_trees_2_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_7 = _a_dec_tree_T_5 + dec_trees_3_a_dec_trees_3_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_9 = _a_dec_tree_T_7 + dec_trees_4_a_dec_trees_4_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_11 = _a_dec_tree_T_9 + dec_trees_5_a_dec_trees_5_data; // @[RAMModel.scala 113:52]
  wire [1:0] _a_dec_tree_T_13 = _a_dec_tree_T_11 + dec_trees_6_a_dec_trees_6_data; // @[RAMModel.scala 113:52]
  wire [1:0] a_dec_tree = _a_dec_tree_T_13 + dec_trees_7_a_dec_trees_7_data; // @[RAMModel.scala 113:52]
  wire [1:0] a_inc_0 = inc_bytes_0_a_inc_bytes_0_data + a_inc_tree; // @[RAMModel.scala 114:37]
  wire [1:0] a_inc_1 = inc_bytes_1_a_inc_bytes_1_data + a_inc_tree; // @[RAMModel.scala 114:37]
  wire [1:0] a_inc_2 = inc_bytes_2_a_inc_bytes_2_data + a_inc_tree; // @[RAMModel.scala 114:37]
  wire [1:0] a_inc_3 = inc_bytes_3_a_inc_bytes_3_data + a_inc_tree; // @[RAMModel.scala 114:37]
  wire [1:0] a_dec_0 = dec_bytes_0_a_dec_bytes_0_data + a_dec_tree; // @[RAMModel.scala 115:37]
  wire [1:0] a_dec_1 = dec_bytes_1_a_dec_bytes_1_data + a_dec_tree; // @[RAMModel.scala 115:37]
  wire [1:0] a_dec_2 = dec_bytes_2_a_dec_bytes_2_data + a_dec_tree; // @[RAMModel.scala 115:37]
  wire [1:0] a_dec_3 = dec_bytes_3_a_dec_bytes_3_data + a_dec_tree; // @[RAMModel.scala 115:37]
  wire  _T_5 = ~reset; // @[RAMModel.scala 119:16]
  wire  _T_11 = a__size <= 4'h2; // @[RAMModel.scala 126:24]
  wire [3:0] _GEN_45 = a__size <= 4'h2 ? a_mask : shadow_wen_x9; // @[RAMModel.scala 126:40 127:27]
  wire [3:0] _GEN_46 = a_first & a__opcode != 3'h5 & a__opcode != 3'h4 ? _GEN_45 : shadow_wen_x9; // @[RAMModel.scala 125:87]
  wire [12:0] _GEN_47 = a_first & a__opcode != 3'h5 & a__opcode != 3'h4 ? a_sizeOH[15:3] : {{5'd0}, inc_trees_wen_x15}; // @[RAMModel.scala 125:87 129:25]
  wire  _T_12 = a__opcode == 3'h0; // @[RAMModel.scala 132:24]
  wire  _T_13 = a__opcode == 3'h1; // @[RAMModel.scala 132:63]
  wire  _T_15 = a__opcode == 3'h2; // @[RAMModel.scala 133:24]
  wire  _T_16 = a__opcode == 3'h0 | a__opcode == 3'h1 | _T_15; // @[RAMModel.scala 132:93]
  wire  _T_17 = a__opcode == 3'h3; // @[RAMModel.scala 133:66]
  wire  _T_18 = _T_16 | a__opcode == 3'h3; // @[RAMModel.scala 133:54]
  wire [1:0] _busy_T_1 = a_inc_0 - a_dec_0; // @[RAMModel.scala 136:33]
  wire  _busy_T_2 = ~a_first; // @[RAMModel.scala 136:47]
  wire [1:0] _GEN_243 = {{1'd0}, _busy_T_2}; // @[RAMModel.scala 136:44]
  wire [1:0] busy = _busy_T_1 - _GEN_243; // @[RAMModel.scala 136:44]
  wire [7:0] byte_ = a__data[7:0]; // @[RAMModel.scala 137:30]
  wire [11:0] _T_34 = {a_addr_hi, 2'h0}; // @[RAMModel.scala 144:58]
  wire [1:0] _busy_T_5 = a_inc_1 - a_dec_1; // @[RAMModel.scala 136:33]
  wire [1:0] busy_1 = _busy_T_5 - _GEN_243; // @[RAMModel.scala 136:44]
  wire [7:0] byte_1 = a__data[15:8]; // @[RAMModel.scala 137:30]
  wire [1:0] _busy_T_9 = a_inc_2 - a_dec_2; // @[RAMModel.scala 136:33]
  wire [1:0] busy_2 = _busy_T_9 - _GEN_243; // @[RAMModel.scala 136:44]
  wire [7:0] byte_2 = a__data[23:16]; // @[RAMModel.scala 137:30]
  wire [1:0] _busy_T_13 = a_inc_3 - a_dec_3; // @[RAMModel.scala 136:33]
  wire [1:0] busy_3 = _busy_T_13 - _GEN_243; // @[RAMModel.scala 136:44]
  wire [7:0] byte_3 = a__data[31:24]; // @[RAMModel.scala 137:30]
  wire [3:0] _GEN_48 = _T_16 | a__opcode == 3'h3 ? a__mask : shadow_wen_x9; // @[RAMModel.scala 133:94 134:22]
  wire  _T_95 = a__opcode == 3'h4; // @[RAMModel.scala 149:24]
  wire [26:0] _T_97 = 27'hfff << a__size; // @[package.scala 234:77]
  wire [11:0] _T_99 = ~_T_97[11:0]; // @[package.scala 234:46]
  wire [3:0] inc_bytes_wen = a_fire ? _GEN_46 : shadow_wen_x9; // @[RAMModel.scala 117:21]
  wire [12:0] inc_trees_wen = a_fire ? _GEN_47 : {{5'd0}, inc_trees_wen_x15}; // @[RAMModel.scala 117:21]
  wire [3:0] shadow_wen = a_fire ? _GEN_48 : shadow_wen_x9; // @[RAMModel.scala 117:21]
  wire [10:0] a_waddr = wipe ? wipeIndex : {{1'd0}, a_addr_hi}; // @[RAMModel.scala 154:24]
  wire  _a_known_old_T = ~shadow_0_valid_a_shadow_0_data; // @[RAMModel.scala 156:44]
  wire  _a_known_old_T_1 = ~shadow_1_valid_a_shadow_1_data; // @[RAMModel.scala 156:44]
  wire  _a_known_old_T_2 = ~shadow_2_valid_a_shadow_2_data; // @[RAMModel.scala 156:44]
  wire  _a_known_old_T_3 = ~shadow_3_valid_a_shadow_3_data; // @[RAMModel.scala 156:44]
  wire [3:0] _a_known_old_T_4 = {_a_known_old_T_3,_a_known_old_T_2,_a_known_old_T_1,_a_known_old_T}; // @[Cat.scala 33:92]
  wire [3:0] _a_known_old_T_5 = _a_known_old_T_4 & a_mask; // @[RAMModel.scala 156:63]
  wire  a_known_old = ~(|_a_known_old_T_5); // @[RAMModel.scala 156:25]
  wire [15:0] alu_io_data_in_lo = {shadow_1_value_a_shadow_1_data,shadow_0_value_a_shadow_0_data}; // @[Cat.scala 33:92]
  wire [15:0] alu_io_data_in_hi = {shadow_3_value_a_shadow_3_data,shadow_2_value_a_shadow_2_data}; // @[Cat.scala 33:92]
  wire [15:0] a_crc_acc = a_first ? 16'h0 : crc_a_crc_acc_MPORT_data; // @[RAMModel.scala 164:26]
  wire [7:0] _a_crc_new_T_1 = a_mask[0] ? shadow_0_value_a_shadow_0_data : 8'h0; // @[RAMModel.scala 165:73]
  wire [7:0] _a_crc_new_T_3 = a_mask[1] ? shadow_1_value_a_shadow_1_data : 8'h0; // @[RAMModel.scala 165:73]
  wire [7:0] _a_crc_new_T_5 = a_mask[2] ? shadow_2_value_a_shadow_2_data : 8'h0; // @[RAMModel.scala 165:73]
  wire [7:0] _a_crc_new_T_7 = a_mask[3] ? shadow_3_value_a_shadow_3_data : 8'h0; // @[RAMModel.scala 165:73]
  wire [47:0] _a_crc_T = {a_crc_acc,_a_crc_new_T_7,_a_crc_new_T_5,_a_crc_new_T_3,_a_crc_new_T_1}; // @[Cat.scala 33:92]
  wire [47:0] _a_crc_T_6 = 48'heaa477170001 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_7 = ^_a_crc_T_6; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_8 = 48'h3fec99390002 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_9 = ^_a_crc_T_8; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_10 = 48'h7fd932720004 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_11 = ^_a_crc_T_10; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_12 = 48'h151613f30008 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_13 = ^_a_crc_T_12; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_14 = 48'h2a2c27e60010 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_15 = ^_a_crc_T_14; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_16 = 48'hbefc38db0020 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_17 = ^_a_crc_T_16; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_18 = 48'h975c06a10040 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_19 = ^_a_crc_T_18; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_20 = 48'hc41c7a550080 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_21 = ^_a_crc_T_20; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_22 = 48'h8838f4aa0100 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_23 = ^_a_crc_T_22; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_24 = 48'hfad59e430200 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_25 = ^_a_crc_T_24; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_26 = 48'hf5ab3c860400 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_27 = ^_a_crc_T_26; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_28 = 48'heb56790c0800 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_29 = ^_a_crc_T_28; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_30 = 48'hd6acf2181000 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_31 = ^_a_crc_T_30; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_32 = 48'h47fd93272000 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_33 = ^_a_crc_T_32; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_34 = 48'h8ffb264e4000 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_35 = ^_a_crc_T_34; // @[CRC.scala 30:63]
  wire [47:0] _a_crc_T_36 = 48'hf5523b8b8000 & _a_crc_T; // @[CRC.scala 30:48]
  wire  _a_crc_T_37 = ^_a_crc_T_36; // @[CRC.scala 30:63]
  wire [7:0] a_crc_lo = {_a_crc_T_21,_a_crc_T_19,_a_crc_T_17,_a_crc_T_15,_a_crc_T_13,_a_crc_T_11,_a_crc_T_9,_a_crc_T_7}; // @[Cat.scala 33:92]
  wire [7:0] a_crc_hi = {_a_crc_T_37,_a_crc_T_35,_a_crc_T_33,_a_crc_T_31,_a_crc_T_29,_a_crc_T_27,_a_crc_T_25,_a_crc_T_23
    }; // @[Cat.scala 33:92]
  wire  _a_crc_valid_T = a_first | crc_valid_a_crc_valid_MPORT_data; // @[RAMModel.scala 167:43]
  wire  amo = _T_15 | _T_17; // @[RAMModel.scala 176:58]
  wire  _data_valid_T_4 = ~amo | a_known_old & _T_11; // @[RAMModel.scala 178:73]
  wire [1:0] _data_T_1 = inc_bytes_0_a_inc_bytes_0_data + 2'h1; // @[RAMModel.scala 186:54]
  wire [1:0] _data_T_3 = inc_bytes_1_a_inc_bytes_1_data + 2'h1; // @[RAMModel.scala 186:54]
  wire [1:0] _data_T_5 = inc_bytes_2_a_inc_bytes_2_data + 2'h1; // @[RAMModel.scala 186:54]
  wire [1:0] _data_T_7 = inc_bytes_3_a_inc_bytes_3_data + 2'h1; // @[RAMModel.scala 186:54]
  wire [1:0] _data_T_9 = inc_trees_0_a_inc_trees_0_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_11 = inc_trees_1_a_inc_trees_1_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_13 = inc_trees_2_a_inc_trees_2_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_15 = inc_trees_3_a_inc_trees_3_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_17 = inc_trees_4_a_inc_trees_4_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_19 = inc_trees_5_a_inc_trees_5_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_21 = inc_trees_6_a_inc_trees_6_data + 2'h1; // @[RAMModel.scala 193:54]
  wire [1:0] _data_T_23 = inc_trees_7_a_inc_trees_7_data + 2'h1; // @[RAMModel.scala 193:54]
  reg [2:0] d_opcode; // @[RAMModel.scala 200:22]
  reg [3:0] d_size; // @[RAMModel.scala 200:22]
  reg [1:0] d_source; // @[RAMModel.scala 200:22]
  reg  d_denied; // @[RAMModel.scala 200:22]
  reg [31:0] d_data; // @[RAMModel.scala 200:22]
  reg  d_fire; // @[RAMModel.scala 201:23]
  wire [24:0] _beats1_decode_T_5 = 25'h3ff << d_size; // @[package.scala 234:77]
  wire [9:0] _beats1_decode_T_7 = ~_beats1_decode_T_5[9:0]; // @[package.scala 234:46]
  wire [7:0] beats1_decode_1 = _beats1_decode_T_7[9:2]; // @[Edges.scala 219:59]
  wire  beats1_opdata_1 = d_opcode[0]; // @[Edges.scala 105:36]
  wire [7:0] beats1_1 = beats1_opdata_1 ? beats1_decode_1 : 8'h0; // @[Edges.scala 220:14]
  reg [7:0] counter_1; // @[Edges.scala 228:27]
  wire [7:0] counter1_1 = counter_1 - 8'h1; // @[Edges.scala 229:28]
  wire  d_first = counter_1 == 8'h0; // @[Edges.scala 230:25]
  wire  d_last = counter_1 == 8'h1 | beats1_1 == 8'h0; // @[Edges.scala 231:37]
  wire [7:0] _count_T_1 = ~counter1_1; // @[Edges.scala 233:27]
  wire [7:0] count_1 = beats1_1 & _count_T_1; // @[Edges.scala 233:25]
  wire [9:0] d_address_inc = {count_1, 2'h0}; // @[Edges.scala 268:29]
  wire [15:0] d_sizeOH = 16'h1 << d_size; // @[OneHot.scala 57:35]
  wire [11:0] _GEN_251 = {{2'd0}, d_address_inc}; // @[RAMModel.scala 206:30]
  wire [11:0] d_address = d_flight_base | _GEN_251; // @[RAMModel.scala 206:30]
  wire [9:0] d_addr_hi = d_address[11:2]; // @[Edges.scala 191:34]
  wire  d_mask_sizeOH_shiftAmount = d_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _d_mask_sizeOH_T_1 = 2'h1 << d_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] d_mask_sizeOH = _d_mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _d_mask_T = d_size >= 4'h2; // @[Misc.scala 205:21]
  wire  d_mask_size = d_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  d_mask_bit = d_flight_base[1]; // @[Misc.scala 209:26]
  wire  d_mask_nbit = ~d_mask_bit; // @[Misc.scala 210:20]
  wire  d_mask_acc = _d_mask_T | d_mask_size & d_mask_nbit; // @[Misc.scala 214:29]
  wire  d_mask_acc_1 = _d_mask_T | d_mask_size & d_mask_bit; // @[Misc.scala 214:29]
  wire  d_mask_size_1 = d_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  d_mask_bit_1 = d_flight_base[0]; // @[Misc.scala 209:26]
  wire  d_mask_nbit_1 = ~d_mask_bit_1; // @[Misc.scala 210:20]
  wire  d_mask_eq_2 = d_mask_nbit & d_mask_nbit_1; // @[Misc.scala 213:27]
  wire  d_mask_acc_2 = d_mask_acc | d_mask_size_1 & d_mask_eq_2; // @[Misc.scala 214:29]
  wire  d_mask_eq_3 = d_mask_nbit & d_mask_bit_1; // @[Misc.scala 213:27]
  wire  d_mask_acc_3 = d_mask_acc | d_mask_size_1 & d_mask_eq_3; // @[Misc.scala 214:29]
  wire  d_mask_eq_4 = d_mask_bit & d_mask_nbit_1; // @[Misc.scala 213:27]
  wire  d_mask_acc_4 = d_mask_acc_1 | d_mask_size_1 & d_mask_eq_4; // @[Misc.scala 214:29]
  wire  d_mask_eq_5 = d_mask_bit & d_mask_bit_1; // @[Misc.scala 213:27]
  wire  d_mask_acc_5 = d_mask_acc_1 | d_mask_size_1 & d_mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] d_mask = {d_mask_acc_5,d_mask_acc_4,d_mask_acc_3,d_mask_acc_2}; // @[Cat.scala 33:92]
  wire [2:0] _d_inc_tree_T = {{1'd0}, inc_trees_0_d_inc_trees_0_data}; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_3 = _d_inc_tree_T[1:0] + inc_trees_1_d_inc_trees_1_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_5 = _d_inc_tree_T_3 + inc_trees_2_d_inc_trees_2_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_7 = _d_inc_tree_T_5 + inc_trees_3_d_inc_trees_3_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_9 = _d_inc_tree_T_7 + inc_trees_4_d_inc_trees_4_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_11 = _d_inc_tree_T_9 + inc_trees_5_d_inc_trees_5_data; // @[RAMModel.scala 216:52]
  wire [1:0] _d_inc_tree_T_13 = _d_inc_tree_T_11 + inc_trees_6_d_inc_trees_6_data; // @[RAMModel.scala 216:52]
  wire [1:0] d_inc_tree = _d_inc_tree_T_13 + inc_trees_7_d_inc_trees_7_data; // @[RAMModel.scala 216:52]
  wire [2:0] _d_dec_tree_T = {{1'd0}, dec_trees_0_d_dec_trees_0_data}; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_3 = _d_dec_tree_T[1:0] + dec_trees_1_d_dec_trees_1_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_5 = _d_dec_tree_T_3 + dec_trees_2_d_dec_trees_2_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_7 = _d_dec_tree_T_5 + dec_trees_3_d_dec_trees_3_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_9 = _d_dec_tree_T_7 + dec_trees_4_d_dec_trees_4_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_11 = _d_dec_tree_T_9 + dec_trees_5_d_dec_trees_5_data; // @[RAMModel.scala 217:52]
  wire [1:0] _d_dec_tree_T_13 = _d_dec_tree_T_11 + dec_trees_6_d_dec_trees_6_data; // @[RAMModel.scala 217:52]
  wire [1:0] d_dec_tree = _d_dec_tree_T_13 + dec_trees_7_d_dec_trees_7_data; // @[RAMModel.scala 217:52]
  wire [1:0] d_inc_0 = inc_bytes_0_d_inc_bytes_0_data + d_inc_tree; // @[RAMModel.scala 218:37]
  wire [1:0] d_inc_1 = inc_bytes_1_d_inc_bytes_1_data + d_inc_tree; // @[RAMModel.scala 218:37]
  wire [1:0] d_inc_2 = inc_bytes_2_d_inc_bytes_2_data + d_inc_tree; // @[RAMModel.scala 218:37]
  wire [1:0] d_inc_3 = inc_bytes_3_d_inc_bytes_3_data + d_inc_tree; // @[RAMModel.scala 218:37]
  wire [1:0] d_dec_0 = dec_bytes_0_d_dec_bytes_0_data + d_dec_tree; // @[RAMModel.scala 219:37]
  wire [1:0] d_dec_1 = dec_bytes_1_d_dec_bytes_1_data + d_dec_tree; // @[RAMModel.scala 219:37]
  wire [1:0] d_dec_2 = dec_bytes_2_d_dec_bytes_2_data + d_dec_tree; // @[RAMModel.scala 219:37]
  wire [1:0] d_dec_3 = dec_bytes_3_d_dec_bytes_3_data + d_dec_tree; // @[RAMModel.scala 219:37]
  reg [15:0] d_crc_reg; // @[RAMModel.scala 224:26]
  wire [15:0] d_crc_acc = d_first ? 16'h0 : d_crc_reg; // @[RAMModel.scala 225:26]
  wire [7:0] _d_crc_new_T_5 = d_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _d_crc_new_T_7 = d_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _d_crc_new_T_9 = d_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [7:0] _d_crc_new_T_11 = d_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 77:12]
  wire [31:0] _d_crc_new_T_12 = {_d_crc_new_T_11,_d_crc_new_T_9,_d_crc_new_T_7,_d_crc_new_T_5}; // @[Cat.scala 33:92]
  wire [31:0] d_crc_new = _d_crc_new_T_12 & d_data; // @[RAMModel.scala 226:50]
  wire [47:0] _d_crc_T = {d_crc_acc,d_crc_new}; // @[Cat.scala 33:92]
  wire [47:0] _d_crc_T_6 = 48'heaa477170001 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_7 = ^_d_crc_T_6; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_8 = 48'h3fec99390002 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_9 = ^_d_crc_T_8; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_10 = 48'h7fd932720004 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_11 = ^_d_crc_T_10; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_12 = 48'h151613f30008 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_13 = ^_d_crc_T_12; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_14 = 48'h2a2c27e60010 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_15 = ^_d_crc_T_14; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_16 = 48'hbefc38db0020 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_17 = ^_d_crc_T_16; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_18 = 48'h975c06a10040 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_19 = ^_d_crc_T_18; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_20 = 48'hc41c7a550080 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_21 = ^_d_crc_T_20; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_22 = 48'h8838f4aa0100 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_23 = ^_d_crc_T_22; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_24 = 48'hfad59e430200 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_25 = ^_d_crc_T_24; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_26 = 48'hf5ab3c860400 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_27 = ^_d_crc_T_26; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_28 = 48'heb56790c0800 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_29 = ^_d_crc_T_28; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_30 = 48'hd6acf2181000 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_31 = ^_d_crc_T_30; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_32 = 48'h47fd93272000 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_33 = ^_d_crc_T_32; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_34 = 48'h8ffb264e4000 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_35 = ^_d_crc_T_34; // @[CRC.scala 30:63]
  wire [47:0] _d_crc_T_36 = 48'hf5523b8b8000 & _d_crc_T; // @[CRC.scala 30:48]
  wire  _d_crc_T_37 = ^_d_crc_T_36; // @[CRC.scala 30:63]
  wire [7:0] d_crc_lo = {_d_crc_T_21,_d_crc_T_19,_d_crc_T_17,_d_crc_T_15,_d_crc_T_13,_d_crc_T_11,_d_crc_T_9,_d_crc_T_7}; // @[Cat.scala 33:92]
  wire [15:0] d_crc = {_d_crc_T_37,_d_crc_T_35,_d_crc_T_33,_d_crc_T_31,_d_crc_T_29,_d_crc_T_27,_d_crc_T_25,_d_crc_T_23,
    d_crc_lo}; // @[Cat.scala 33:92]
  wire  _d_crc_valid_T = crc_valid_d_crc_valid_MPORT_data; // @[RAMModel.scala 229:28]
  reg  d_crc_valid_r; // @[Reg.scala 19:16]
  wire  _GEN_152 = d_first ? _d_crc_valid_T : d_crc_valid_r; // @[Reg.scala 19:16 20:{18,22}]
  wire [15:0] _d_crc_check_T = crc_d_crc_check_MPORT_data; // @[RAMModel.scala 230:28]
  reg [15:0] d_crc_check_r; // @[Reg.scala 19:16]
  wire [15:0] _GEN_153 = d_first ? _d_crc_check_T : d_crc_check_r; // @[Reg.scala 19:16 20:{18,22}]
  wire  _T_147 = d_flight_opcode == 3'h5; // @[RAMModel.scala 243:31]
  wire [3:0] _GEN_154 = d_size <= 4'h2 ? d_mask : shadow_wen_x9; // @[RAMModel.scala 249:40 250:27]
  wire [26:0] _d_bits_T_1 = 27'hfff << d_size; // @[package.scala 234:77]
  wire [11:0] d_bits = ~_d_bits_T_1[11:0]; // @[package.scala 234:46]
  wire [3:0] _GEN_159 = d_last & d_flight_opcode != 3'h5 & d_flight_opcode != 3'h4 ? _GEN_154 : shadow_wen_x9; // @[RAMModel.scala 248:100]
  wire [12:0] _GEN_160 = d_last & d_flight_opcode != 3'h5 & d_flight_opcode != 3'h4 ? d_sizeOH[15:3] : {{5'd0},
    inc_trees_wen_x15}; // @[RAMModel.scala 248:100 252:25]
  wire  _T_157 = d_flight_opcode == 3'h0; // @[RAMModel.scala 265:31]
  wire  _T_158 = d_flight_opcode == 3'h1; // @[RAMModel.scala 265:77]
  wire  _T_159 = d_flight_opcode == 3'h0 | d_flight_opcode == 3'h1; // @[RAMModel.scala 265:58]
  wire  _T_179 = d_flight_opcode == 3'h4; // @[RAMModel.scala 273:31]
  wire  _T_180 = d_flight_opcode == 3'h2; // @[RAMModel.scala 273:69]
  wire  _T_182 = d_flight_opcode == 3'h3; // @[RAMModel.scala 273:118]
  wire  _T_183 = d_flight_opcode == 3'h4 | d_flight_opcode == 3'h2 | d_flight_opcode == 3'h3; // @[RAMModel.scala 273:99]
  wire [7:0] got = d_data[7:0]; // @[RAMModel.scala 276:29]
  wire [11:0] d_addr = {d_addr_hi, 2'h0}; // @[RAMModel.scala 279:38]
  wire  shadow_valid = shadow_0_valid_d_shadow_0_data;
  wire  _T_202 = ~shadow_valid; // @[RAMModel.scala 285:21]
  wire  _T_205 = d_inc_0 != d_dec_0; // @[RAMModel.scala 287:37]
  wire [7:0] shadow_value = shadow_0_value_d_shadow_0_data;
  wire [7:0] got_1 = d_data[15:8]; // @[RAMModel.scala 276:29]
  wire [11:0] d_addr_1 = d_addr | 12'h1; // @[RAMModel.scala 279:47]
  wire  shadow_4_valid = shadow_1_valid_d_shadow_1_data;
  wire  _T_244 = ~shadow_4_valid; // @[RAMModel.scala 285:21]
  wire  _T_247 = d_inc_1 != d_dec_1; // @[RAMModel.scala 287:37]
  wire [7:0] shadow_4_value = shadow_1_value_d_shadow_1_data;
  wire [7:0] got_2 = d_data[23:16]; // @[RAMModel.scala 276:29]
  wire [11:0] d_addr_2 = d_addr | 12'h2; // @[RAMModel.scala 279:47]
  wire  shadow_5_valid = shadow_2_valid_d_shadow_2_data;
  wire  _T_286 = ~shadow_5_valid; // @[RAMModel.scala 285:21]
  wire  _T_289 = d_inc_2 != d_dec_2; // @[RAMModel.scala 287:37]
  wire [7:0] shadow_5_value = shadow_2_value_d_shadow_2_data;
  wire [7:0] got_3 = d_data[31:24]; // @[RAMModel.scala 276:29]
  wire [11:0] d_addr_3 = d_addr | 12'h3; // @[RAMModel.scala 279:47]
  wire  shadow_6_valid = shadow_3_valid_d_shadow_3_data;
  wire  _T_328 = ~shadow_6_valid; // @[RAMModel.scala 285:21]
  wire  _T_331 = d_inc_3 != d_dec_3; // @[RAMModel.scala 287:37]
  wire [7:0] shadow_6_value = shadow_3_value_d_shadow_3_data;
  wire  _T_358 = _T_180 | _T_182; // @[RAMModel.scala 304:61]
  wire  _T_364 = ~d_denied; // @[RAMModel.scala 312:19]
  wire [3:0] dec_bytes_wen = d_fire ? _GEN_159 : shadow_wen_x9; // @[RAMModel.scala 235:21]
  wire [12:0] dec_trees_wen = d_fire ? _GEN_160 : {{5'd0}, inc_trees_wen_x15}; // @[RAMModel.scala 235:21]
  wire [10:0] d_waddr = wipe ? wipeIndex : {{1'd0}, d_addr_hi}; // @[RAMModel.scala 318:24]
  wire [1:0] _data_T_25 = dec_bytes_0_d_dec_bytes_0_data + 2'h1; // @[RAMModel.scala 320:54]
  wire [1:0] _data_T_27 = dec_bytes_1_d_dec_bytes_1_data + 2'h1; // @[RAMModel.scala 320:54]
  wire [1:0] _data_T_29 = dec_bytes_2_d_dec_bytes_2_data + 2'h1; // @[RAMModel.scala 320:54]
  wire [1:0] _data_T_31 = dec_bytes_3_d_dec_bytes_3_data + 2'h1; // @[RAMModel.scala 320:54]
  wire [1:0] _data_T_33 = dec_trees_0_d_dec_trees_0_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_35 = dec_trees_1_d_dec_trees_1_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_37 = dec_trees_2_d_dec_trees_2_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_39 = dec_trees_3_d_dec_trees_3_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_41 = dec_trees_4_d_dec_trees_4_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_43 = dec_trees_5_d_dec_trees_5_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_45 = dec_trees_6_d_dec_trees_6_data + 2'h1; // @[RAMModel.scala 327:54]
  wire [1:0] _data_T_47 = dec_trees_7_d_dec_trees_7_data + 2'h1; // @[RAMModel.scala 327:54]
  wire  _GEN_256 = a_fire & _T_18 & a__mask[0]; // @[RAMModel.scala 139:21]
  wire  _GEN_272 = a_fire & _T_18 & a__mask[1]; // @[RAMModel.scala 139:21]
  wire  _GEN_288 = a_fire & _T_18 & a__mask[2]; // @[RAMModel.scala 139:21]
  wire  _GEN_304 = a_fire & _T_18 & a__mask[3]; // @[RAMModel.scala 139:21]
  wire  _GEN_328 = d_fire & _T_159; // @[RAMModel.scala 266:18]
  wire  _GEN_339 = d_fire & _T_183; // @[RAMModel.scala 274:18]
  wire  _GEN_345 = _GEN_339 & d_mask[0]; // @[RAMModel.scala 280:21]
  wire  _GEN_363 = _GEN_345 & ~_T_202; // @[RAMModel.scala 288:23]
  wire  _GEN_370 = _GEN_363 & ~_T_205; // @[RAMModel.scala 292:23]
  wire  _GEN_379 = _GEN_370 & _T_364; // @[RAMModel.scala 296:23]
  wire  _GEN_409 = _GEN_339 & d_mask[1]; // @[RAMModel.scala 280:21]
  wire  _GEN_427 = _GEN_409 & ~_T_244; // @[RAMModel.scala 288:23]
  wire  _GEN_434 = _GEN_427 & ~_T_247; // @[RAMModel.scala 292:23]
  wire  _GEN_443 = _GEN_434 & _T_364; // @[RAMModel.scala 296:23]
  wire  _GEN_473 = _GEN_339 & d_mask[2]; // @[RAMModel.scala 280:21]
  wire  _GEN_491 = _GEN_473 & ~_T_286; // @[RAMModel.scala 288:23]
  wire  _GEN_498 = _GEN_491 & ~_T_289; // @[RAMModel.scala 292:23]
  wire  _GEN_507 = _GEN_498 & _T_364; // @[RAMModel.scala 296:23]
  wire  _GEN_537 = _GEN_339 & d_mask[3]; // @[RAMModel.scala 280:21]
  wire  _GEN_555 = _GEN_537 & ~_T_328; // @[RAMModel.scala 288:23]
  wire  _GEN_562 = _GEN_555 & ~_T_331; // @[RAMModel.scala 292:23]
  wire  _GEN_571 = _GEN_562 & _T_364; // @[RAMModel.scala 296:23]
  wire  _GEN_601 = d_fire & _T_358 & d_last; // @[RAMModel.scala 311:19]
  TLMonitor_3 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Atomics_1 alu ( // @[RAMModel.scala 157:23]
    .io_a_opcode(alu_io_a_opcode),
    .io_a_mask(alu_io_a_mask),
    .io_a_data(alu_io_a_data),
    .io_data_in(alu_io_data_in),
    .io_data_out(alu_io_data_out)
  );
  assign shadow_0_valid_a_shadow_0_en = 1'h1;
  assign shadow_0_valid_a_shadow_0_addr = a_waddr[9:0];
  assign shadow_0_valid_a_shadow_0_data = shadow_0_valid[shadow_0_valid_a_shadow_0_addr]; // @[RAMModel.scala 69:45]
  assign shadow_0_valid_d_shadow_0_en = 1'h1;
  assign shadow_0_valid_d_shadow_0_addr = d_address[11:2];
  assign shadow_0_valid_d_shadow_0_data = shadow_0_valid[shadow_0_valid_d_shadow_0_addr]; // @[RAMModel.scala 69:45]
  assign shadow_0_valid_MPORT_2_data = wipe ? 1'h0 : _data_valid_T_4;
  assign shadow_0_valid_MPORT_2_addr = a_waddr[9:0];
  assign shadow_0_valid_MPORT_2_mask = 1'h1;
  assign shadow_0_valid_MPORT_2_en = shadow_wen[0];
  assign shadow_0_value_a_shadow_0_en = 1'h1;
  assign shadow_0_value_a_shadow_0_addr = a_waddr[9:0];
  assign shadow_0_value_a_shadow_0_data = shadow_0_value[shadow_0_value_a_shadow_0_addr]; // @[RAMModel.scala 69:45]
  assign shadow_0_value_d_shadow_0_en = 1'h1;
  assign shadow_0_value_d_shadow_0_addr = d_address[11:2];
  assign shadow_0_value_d_shadow_0_data = shadow_0_value[shadow_0_value_d_shadow_0_addr]; // @[RAMModel.scala 69:45]
  assign shadow_0_value_MPORT_2_data = alu_io_data_out[7:0];
  assign shadow_0_value_MPORT_2_addr = a_waddr[9:0];
  assign shadow_0_value_MPORT_2_mask = 1'h1;
  assign shadow_0_value_MPORT_2_en = shadow_wen[0];
  assign shadow_1_valid_a_shadow_1_en = 1'h1;
  assign shadow_1_valid_a_shadow_1_addr = a_waddr[9:0];
  assign shadow_1_valid_a_shadow_1_data = shadow_1_valid[shadow_1_valid_a_shadow_1_addr]; // @[RAMModel.scala 69:45]
  assign shadow_1_valid_d_shadow_1_en = 1'h1;
  assign shadow_1_valid_d_shadow_1_addr = d_address[11:2];
  assign shadow_1_valid_d_shadow_1_data = shadow_1_valid[shadow_1_valid_d_shadow_1_addr]; // @[RAMModel.scala 69:45]
  assign shadow_1_valid_MPORT_3_data = wipe ? 1'h0 : _data_valid_T_4;
  assign shadow_1_valid_MPORT_3_addr = a_waddr[9:0];
  assign shadow_1_valid_MPORT_3_mask = 1'h1;
  assign shadow_1_valid_MPORT_3_en = shadow_wen[1];
  assign shadow_1_value_a_shadow_1_en = 1'h1;
  assign shadow_1_value_a_shadow_1_addr = a_waddr[9:0];
  assign shadow_1_value_a_shadow_1_data = shadow_1_value[shadow_1_value_a_shadow_1_addr]; // @[RAMModel.scala 69:45]
  assign shadow_1_value_d_shadow_1_en = 1'h1;
  assign shadow_1_value_d_shadow_1_addr = d_address[11:2];
  assign shadow_1_value_d_shadow_1_data = shadow_1_value[shadow_1_value_d_shadow_1_addr]; // @[RAMModel.scala 69:45]
  assign shadow_1_value_MPORT_3_data = alu_io_data_out[15:8];
  assign shadow_1_value_MPORT_3_addr = a_waddr[9:0];
  assign shadow_1_value_MPORT_3_mask = 1'h1;
  assign shadow_1_value_MPORT_3_en = shadow_wen[1];
  assign shadow_2_valid_a_shadow_2_en = 1'h1;
  assign shadow_2_valid_a_shadow_2_addr = a_waddr[9:0];
  assign shadow_2_valid_a_shadow_2_data = shadow_2_valid[shadow_2_valid_a_shadow_2_addr]; // @[RAMModel.scala 69:45]
  assign shadow_2_valid_d_shadow_2_en = 1'h1;
  assign shadow_2_valid_d_shadow_2_addr = d_address[11:2];
  assign shadow_2_valid_d_shadow_2_data = shadow_2_valid[shadow_2_valid_d_shadow_2_addr]; // @[RAMModel.scala 69:45]
  assign shadow_2_valid_MPORT_4_data = wipe ? 1'h0 : _data_valid_T_4;
  assign shadow_2_valid_MPORT_4_addr = a_waddr[9:0];
  assign shadow_2_valid_MPORT_4_mask = 1'h1;
  assign shadow_2_valid_MPORT_4_en = shadow_wen[2];
  assign shadow_2_value_a_shadow_2_en = 1'h1;
  assign shadow_2_value_a_shadow_2_addr = a_waddr[9:0];
  assign shadow_2_value_a_shadow_2_data = shadow_2_value[shadow_2_value_a_shadow_2_addr]; // @[RAMModel.scala 69:45]
  assign shadow_2_value_d_shadow_2_en = 1'h1;
  assign shadow_2_value_d_shadow_2_addr = d_address[11:2];
  assign shadow_2_value_d_shadow_2_data = shadow_2_value[shadow_2_value_d_shadow_2_addr]; // @[RAMModel.scala 69:45]
  assign shadow_2_value_MPORT_4_data = alu_io_data_out[23:16];
  assign shadow_2_value_MPORT_4_addr = a_waddr[9:0];
  assign shadow_2_value_MPORT_4_mask = 1'h1;
  assign shadow_2_value_MPORT_4_en = shadow_wen[2];
  assign shadow_3_valid_a_shadow_3_en = 1'h1;
  assign shadow_3_valid_a_shadow_3_addr = a_waddr[9:0];
  assign shadow_3_valid_a_shadow_3_data = shadow_3_valid[shadow_3_valid_a_shadow_3_addr]; // @[RAMModel.scala 69:45]
  assign shadow_3_valid_d_shadow_3_en = 1'h1;
  assign shadow_3_valid_d_shadow_3_addr = d_address[11:2];
  assign shadow_3_valid_d_shadow_3_data = shadow_3_valid[shadow_3_valid_d_shadow_3_addr]; // @[RAMModel.scala 69:45]
  assign shadow_3_valid_MPORT_5_data = wipe ? 1'h0 : _data_valid_T_4;
  assign shadow_3_valid_MPORT_5_addr = a_waddr[9:0];
  assign shadow_3_valid_MPORT_5_mask = 1'h1;
  assign shadow_3_valid_MPORT_5_en = shadow_wen[3];
  assign shadow_3_value_a_shadow_3_en = 1'h1;
  assign shadow_3_value_a_shadow_3_addr = a_waddr[9:0];
  assign shadow_3_value_a_shadow_3_data = shadow_3_value[shadow_3_value_a_shadow_3_addr]; // @[RAMModel.scala 69:45]
  assign shadow_3_value_d_shadow_3_en = 1'h1;
  assign shadow_3_value_d_shadow_3_addr = d_address[11:2];
  assign shadow_3_value_d_shadow_3_data = shadow_3_value[shadow_3_value_d_shadow_3_addr]; // @[RAMModel.scala 69:45]
  assign shadow_3_value_MPORT_5_data = alu_io_data_out[31:24];
  assign shadow_3_value_MPORT_5_addr = a_waddr[9:0];
  assign shadow_3_value_MPORT_5_mask = 1'h1;
  assign shadow_3_value_MPORT_5_en = shadow_wen[3];
  assign inc_bytes_0_a_inc_bytes_0_en = 1'h1;
  assign inc_bytes_0_a_inc_bytes_0_addr = a_address[11:2];
  assign inc_bytes_0_a_inc_bytes_0_data = inc_bytes_0[inc_bytes_0_a_inc_bytes_0_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_0_d_inc_bytes_0_en = 1'h1;
  assign inc_bytes_0_d_inc_bytes_0_addr = d_address[11:2];
  assign inc_bytes_0_d_inc_bytes_0_data = inc_bytes_0[inc_bytes_0_d_inc_bytes_0_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_0_MPORT_6_data = wipe ? 2'h0 : _data_T_1;
  assign inc_bytes_0_MPORT_6_addr = a_waddr[9:0];
  assign inc_bytes_0_MPORT_6_mask = 1'h1;
  assign inc_bytes_0_MPORT_6_en = inc_bytes_wen[0];
  assign inc_bytes_1_a_inc_bytes_1_en = 1'h1;
  assign inc_bytes_1_a_inc_bytes_1_addr = a_address[11:2];
  assign inc_bytes_1_a_inc_bytes_1_data = inc_bytes_1[inc_bytes_1_a_inc_bytes_1_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_1_d_inc_bytes_1_en = 1'h1;
  assign inc_bytes_1_d_inc_bytes_1_addr = d_address[11:2];
  assign inc_bytes_1_d_inc_bytes_1_data = inc_bytes_1[inc_bytes_1_d_inc_bytes_1_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_1_MPORT_7_data = wipe ? 2'h0 : _data_T_3;
  assign inc_bytes_1_MPORT_7_addr = a_waddr[9:0];
  assign inc_bytes_1_MPORT_7_mask = 1'h1;
  assign inc_bytes_1_MPORT_7_en = inc_bytes_wen[1];
  assign inc_bytes_2_a_inc_bytes_2_en = 1'h1;
  assign inc_bytes_2_a_inc_bytes_2_addr = a_address[11:2];
  assign inc_bytes_2_a_inc_bytes_2_data = inc_bytes_2[inc_bytes_2_a_inc_bytes_2_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_2_d_inc_bytes_2_en = 1'h1;
  assign inc_bytes_2_d_inc_bytes_2_addr = d_address[11:2];
  assign inc_bytes_2_d_inc_bytes_2_data = inc_bytes_2[inc_bytes_2_d_inc_bytes_2_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_2_MPORT_8_data = wipe ? 2'h0 : _data_T_5;
  assign inc_bytes_2_MPORT_8_addr = a_waddr[9:0];
  assign inc_bytes_2_MPORT_8_mask = 1'h1;
  assign inc_bytes_2_MPORT_8_en = inc_bytes_wen[2];
  assign inc_bytes_3_a_inc_bytes_3_en = 1'h1;
  assign inc_bytes_3_a_inc_bytes_3_addr = a_address[11:2];
  assign inc_bytes_3_a_inc_bytes_3_data = inc_bytes_3[inc_bytes_3_a_inc_bytes_3_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_3_d_inc_bytes_3_en = 1'h1;
  assign inc_bytes_3_d_inc_bytes_3_addr = d_address[11:2];
  assign inc_bytes_3_d_inc_bytes_3_data = inc_bytes_3[inc_bytes_3_d_inc_bytes_3_addr]; // @[RAMModel.scala 70:48]
  assign inc_bytes_3_MPORT_9_data = wipe ? 2'h0 : _data_T_7;
  assign inc_bytes_3_MPORT_9_addr = a_waddr[9:0];
  assign inc_bytes_3_MPORT_9_mask = 1'h1;
  assign inc_bytes_3_MPORT_9_en = inc_bytes_wen[3];
  assign dec_bytes_0_a_dec_bytes_0_en = 1'h1;
  assign dec_bytes_0_a_dec_bytes_0_addr = a_address[11:2];
  assign dec_bytes_0_a_dec_bytes_0_data = dec_bytes_0[dec_bytes_0_a_dec_bytes_0_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_0_d_dec_bytes_0_en = 1'h1;
  assign dec_bytes_0_d_dec_bytes_0_addr = d_address[11:2];
  assign dec_bytes_0_d_dec_bytes_0_data = dec_bytes_0[dec_bytes_0_d_dec_bytes_0_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_0_MPORT_18_data = wipe ? 2'h0 : _data_T_25;
  assign dec_bytes_0_MPORT_18_addr = d_waddr[9:0];
  assign dec_bytes_0_MPORT_18_mask = 1'h1;
  assign dec_bytes_0_MPORT_18_en = dec_bytes_wen[0];
  assign dec_bytes_1_a_dec_bytes_1_en = 1'h1;
  assign dec_bytes_1_a_dec_bytes_1_addr = a_address[11:2];
  assign dec_bytes_1_a_dec_bytes_1_data = dec_bytes_1[dec_bytes_1_a_dec_bytes_1_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_1_d_dec_bytes_1_en = 1'h1;
  assign dec_bytes_1_d_dec_bytes_1_addr = d_address[11:2];
  assign dec_bytes_1_d_dec_bytes_1_data = dec_bytes_1[dec_bytes_1_d_dec_bytes_1_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_1_MPORT_19_data = wipe ? 2'h0 : _data_T_27;
  assign dec_bytes_1_MPORT_19_addr = d_waddr[9:0];
  assign dec_bytes_1_MPORT_19_mask = 1'h1;
  assign dec_bytes_1_MPORT_19_en = dec_bytes_wen[1];
  assign dec_bytes_2_a_dec_bytes_2_en = 1'h1;
  assign dec_bytes_2_a_dec_bytes_2_addr = a_address[11:2];
  assign dec_bytes_2_a_dec_bytes_2_data = dec_bytes_2[dec_bytes_2_a_dec_bytes_2_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_2_d_dec_bytes_2_en = 1'h1;
  assign dec_bytes_2_d_dec_bytes_2_addr = d_address[11:2];
  assign dec_bytes_2_d_dec_bytes_2_data = dec_bytes_2[dec_bytes_2_d_dec_bytes_2_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_2_MPORT_20_data = wipe ? 2'h0 : _data_T_29;
  assign dec_bytes_2_MPORT_20_addr = d_waddr[9:0];
  assign dec_bytes_2_MPORT_20_mask = 1'h1;
  assign dec_bytes_2_MPORT_20_en = dec_bytes_wen[2];
  assign dec_bytes_3_a_dec_bytes_3_en = 1'h1;
  assign dec_bytes_3_a_dec_bytes_3_addr = a_address[11:2];
  assign dec_bytes_3_a_dec_bytes_3_data = dec_bytes_3[dec_bytes_3_a_dec_bytes_3_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_3_d_dec_bytes_3_en = 1'h1;
  assign dec_bytes_3_d_dec_bytes_3_addr = d_address[11:2];
  assign dec_bytes_3_d_dec_bytes_3_data = dec_bytes_3[dec_bytes_3_d_dec_bytes_3_addr]; // @[RAMModel.scala 71:48]
  assign dec_bytes_3_MPORT_21_data = wipe ? 2'h0 : _data_T_31;
  assign dec_bytes_3_MPORT_21_addr = d_waddr[9:0];
  assign dec_bytes_3_MPORT_21_mask = 1'h1;
  assign dec_bytes_3_MPORT_21_en = dec_bytes_wen[3];
  assign inc_trees_0_a_inc_trees_0_en = 1'h1;
  assign inc_trees_0_a_inc_trees_0_addr = a_addr_hi[9:1];
  assign inc_trees_0_a_inc_trees_0_data = inc_trees_0[inc_trees_0_a_inc_trees_0_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_0_d_inc_trees_0_en = 1'h1;
  assign inc_trees_0_d_inc_trees_0_addr = d_addr_hi[9:1];
  assign inc_trees_0_d_inc_trees_0_data = inc_trees_0[inc_trees_0_d_inc_trees_0_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_0_MPORT_10_data = wipe ? 2'h0 : _data_T_9;
  assign inc_trees_0_MPORT_10_addr = a_waddr[9:1];
  assign inc_trees_0_MPORT_10_mask = 1'h1;
  assign inc_trees_0_MPORT_10_en = inc_trees_wen[0];
  assign inc_trees_1_a_inc_trees_1_en = 1'h1;
  assign inc_trees_1_a_inc_trees_1_addr = a_addr_hi[9:2];
  assign inc_trees_1_a_inc_trees_1_data = inc_trees_1[inc_trees_1_a_inc_trees_1_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_1_d_inc_trees_1_en = 1'h1;
  assign inc_trees_1_d_inc_trees_1_addr = d_addr_hi[9:2];
  assign inc_trees_1_d_inc_trees_1_data = inc_trees_1[inc_trees_1_d_inc_trees_1_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_1_MPORT_11_data = wipe ? 2'h0 : _data_T_11;
  assign inc_trees_1_MPORT_11_addr = a_waddr[9:2];
  assign inc_trees_1_MPORT_11_mask = 1'h1;
  assign inc_trees_1_MPORT_11_en = inc_trees_wen[1];
  assign inc_trees_2_a_inc_trees_2_en = 1'h1;
  assign inc_trees_2_a_inc_trees_2_addr = a_addr_hi[9:3];
  assign inc_trees_2_a_inc_trees_2_data = inc_trees_2[inc_trees_2_a_inc_trees_2_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_2_d_inc_trees_2_en = 1'h1;
  assign inc_trees_2_d_inc_trees_2_addr = d_addr_hi[9:3];
  assign inc_trees_2_d_inc_trees_2_data = inc_trees_2[inc_trees_2_d_inc_trees_2_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_2_MPORT_12_data = wipe ? 2'h0 : _data_T_13;
  assign inc_trees_2_MPORT_12_addr = a_waddr[9:3];
  assign inc_trees_2_MPORT_12_mask = 1'h1;
  assign inc_trees_2_MPORT_12_en = inc_trees_wen[2];
  assign inc_trees_3_a_inc_trees_3_en = 1'h1;
  assign inc_trees_3_a_inc_trees_3_addr = a_addr_hi[9:4];
  assign inc_trees_3_a_inc_trees_3_data = inc_trees_3[inc_trees_3_a_inc_trees_3_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_3_d_inc_trees_3_en = 1'h1;
  assign inc_trees_3_d_inc_trees_3_addr = d_addr_hi[9:4];
  assign inc_trees_3_d_inc_trees_3_data = inc_trees_3[inc_trees_3_d_inc_trees_3_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_3_MPORT_13_data = wipe ? 2'h0 : _data_T_15;
  assign inc_trees_3_MPORT_13_addr = a_waddr[9:4];
  assign inc_trees_3_MPORT_13_mask = 1'h1;
  assign inc_trees_3_MPORT_13_en = inc_trees_wen[3];
  assign inc_trees_4_a_inc_trees_4_en = 1'h1;
  assign inc_trees_4_a_inc_trees_4_addr = a_addr_hi[9:5];
  assign inc_trees_4_a_inc_trees_4_data = inc_trees_4[inc_trees_4_a_inc_trees_4_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_4_d_inc_trees_4_en = 1'h1;
  assign inc_trees_4_d_inc_trees_4_addr = d_addr_hi[9:5];
  assign inc_trees_4_d_inc_trees_4_data = inc_trees_4[inc_trees_4_d_inc_trees_4_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_4_MPORT_14_data = wipe ? 2'h0 : _data_T_17;
  assign inc_trees_4_MPORT_14_addr = a_waddr[9:5];
  assign inc_trees_4_MPORT_14_mask = 1'h1;
  assign inc_trees_4_MPORT_14_en = inc_trees_wen[4];
  assign inc_trees_5_a_inc_trees_5_en = 1'h1;
  assign inc_trees_5_a_inc_trees_5_addr = a_addr_hi[9:6];
  assign inc_trees_5_a_inc_trees_5_data = inc_trees_5[inc_trees_5_a_inc_trees_5_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_5_d_inc_trees_5_en = 1'h1;
  assign inc_trees_5_d_inc_trees_5_addr = d_addr_hi[9:6];
  assign inc_trees_5_d_inc_trees_5_data = inc_trees_5[inc_trees_5_d_inc_trees_5_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_5_MPORT_15_data = wipe ? 2'h0 : _data_T_19;
  assign inc_trees_5_MPORT_15_addr = a_waddr[9:6];
  assign inc_trees_5_MPORT_15_mask = 1'h1;
  assign inc_trees_5_MPORT_15_en = inc_trees_wen[5];
  assign inc_trees_6_a_inc_trees_6_en = 1'h1;
  assign inc_trees_6_a_inc_trees_6_addr = a_addr_hi[9:7];
  assign inc_trees_6_a_inc_trees_6_data = inc_trees_6[inc_trees_6_a_inc_trees_6_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_6_d_inc_trees_6_en = 1'h1;
  assign inc_trees_6_d_inc_trees_6_addr = d_addr_hi[9:7];
  assign inc_trees_6_d_inc_trees_6_data = inc_trees_6[inc_trees_6_d_inc_trees_6_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_6_MPORT_16_data = wipe ? 2'h0 : _data_T_21;
  assign inc_trees_6_MPORT_16_addr = a_waddr[9:7];
  assign inc_trees_6_MPORT_16_mask = 1'h1;
  assign inc_trees_6_MPORT_16_en = inc_trees_wen[6];
  assign inc_trees_7_a_inc_trees_7_en = 1'h1;
  assign inc_trees_7_a_inc_trees_7_addr = a_addr_hi[9:8];
  assign inc_trees_7_a_inc_trees_7_data = inc_trees_7[inc_trees_7_a_inc_trees_7_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_7_d_inc_trees_7_en = 1'h1;
  assign inc_trees_7_d_inc_trees_7_addr = d_addr_hi[9:8];
  assign inc_trees_7_d_inc_trees_7_data = inc_trees_7[inc_trees_7_d_inc_trees_7_addr]; // @[RAMModel.scala 72:56]
  assign inc_trees_7_MPORT_17_data = wipe ? 2'h0 : _data_T_23;
  assign inc_trees_7_MPORT_17_addr = a_waddr[9:8];
  assign inc_trees_7_MPORT_17_mask = 1'h1;
  assign inc_trees_7_MPORT_17_en = inc_trees_wen[7];
  assign dec_trees_0_a_dec_trees_0_en = 1'h1;
  assign dec_trees_0_a_dec_trees_0_addr = a_addr_hi[9:1];
  assign dec_trees_0_a_dec_trees_0_data = dec_trees_0[dec_trees_0_a_dec_trees_0_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_0_d_dec_trees_0_en = 1'h1;
  assign dec_trees_0_d_dec_trees_0_addr = d_addr_hi[9:1];
  assign dec_trees_0_d_dec_trees_0_data = dec_trees_0[dec_trees_0_d_dec_trees_0_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_0_MPORT_22_data = wipe ? 2'h0 : _data_T_33;
  assign dec_trees_0_MPORT_22_addr = d_waddr[9:1];
  assign dec_trees_0_MPORT_22_mask = 1'h1;
  assign dec_trees_0_MPORT_22_en = dec_trees_wen[0];
  assign dec_trees_1_a_dec_trees_1_en = 1'h1;
  assign dec_trees_1_a_dec_trees_1_addr = a_addr_hi[9:2];
  assign dec_trees_1_a_dec_trees_1_data = dec_trees_1[dec_trees_1_a_dec_trees_1_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_1_d_dec_trees_1_en = 1'h1;
  assign dec_trees_1_d_dec_trees_1_addr = d_addr_hi[9:2];
  assign dec_trees_1_d_dec_trees_1_data = dec_trees_1[dec_trees_1_d_dec_trees_1_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_1_MPORT_23_data = wipe ? 2'h0 : _data_T_35;
  assign dec_trees_1_MPORT_23_addr = d_waddr[9:2];
  assign dec_trees_1_MPORT_23_mask = 1'h1;
  assign dec_trees_1_MPORT_23_en = dec_trees_wen[1];
  assign dec_trees_2_a_dec_trees_2_en = 1'h1;
  assign dec_trees_2_a_dec_trees_2_addr = a_addr_hi[9:3];
  assign dec_trees_2_a_dec_trees_2_data = dec_trees_2[dec_trees_2_a_dec_trees_2_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_2_d_dec_trees_2_en = 1'h1;
  assign dec_trees_2_d_dec_trees_2_addr = d_addr_hi[9:3];
  assign dec_trees_2_d_dec_trees_2_data = dec_trees_2[dec_trees_2_d_dec_trees_2_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_2_MPORT_24_data = wipe ? 2'h0 : _data_T_37;
  assign dec_trees_2_MPORT_24_addr = d_waddr[9:3];
  assign dec_trees_2_MPORT_24_mask = 1'h1;
  assign dec_trees_2_MPORT_24_en = dec_trees_wen[2];
  assign dec_trees_3_a_dec_trees_3_en = 1'h1;
  assign dec_trees_3_a_dec_trees_3_addr = a_addr_hi[9:4];
  assign dec_trees_3_a_dec_trees_3_data = dec_trees_3[dec_trees_3_a_dec_trees_3_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_3_d_dec_trees_3_en = 1'h1;
  assign dec_trees_3_d_dec_trees_3_addr = d_addr_hi[9:4];
  assign dec_trees_3_d_dec_trees_3_data = dec_trees_3[dec_trees_3_d_dec_trees_3_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_3_MPORT_25_data = wipe ? 2'h0 : _data_T_39;
  assign dec_trees_3_MPORT_25_addr = d_waddr[9:4];
  assign dec_trees_3_MPORT_25_mask = 1'h1;
  assign dec_trees_3_MPORT_25_en = dec_trees_wen[3];
  assign dec_trees_4_a_dec_trees_4_en = 1'h1;
  assign dec_trees_4_a_dec_trees_4_addr = a_addr_hi[9:5];
  assign dec_trees_4_a_dec_trees_4_data = dec_trees_4[dec_trees_4_a_dec_trees_4_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_4_d_dec_trees_4_en = 1'h1;
  assign dec_trees_4_d_dec_trees_4_addr = d_addr_hi[9:5];
  assign dec_trees_4_d_dec_trees_4_data = dec_trees_4[dec_trees_4_d_dec_trees_4_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_4_MPORT_26_data = wipe ? 2'h0 : _data_T_41;
  assign dec_trees_4_MPORT_26_addr = d_waddr[9:5];
  assign dec_trees_4_MPORT_26_mask = 1'h1;
  assign dec_trees_4_MPORT_26_en = dec_trees_wen[4];
  assign dec_trees_5_a_dec_trees_5_en = 1'h1;
  assign dec_trees_5_a_dec_trees_5_addr = a_addr_hi[9:6];
  assign dec_trees_5_a_dec_trees_5_data = dec_trees_5[dec_trees_5_a_dec_trees_5_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_5_d_dec_trees_5_en = 1'h1;
  assign dec_trees_5_d_dec_trees_5_addr = d_addr_hi[9:6];
  assign dec_trees_5_d_dec_trees_5_data = dec_trees_5[dec_trees_5_d_dec_trees_5_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_5_MPORT_27_data = wipe ? 2'h0 : _data_T_43;
  assign dec_trees_5_MPORT_27_addr = d_waddr[9:6];
  assign dec_trees_5_MPORT_27_mask = 1'h1;
  assign dec_trees_5_MPORT_27_en = dec_trees_wen[5];
  assign dec_trees_6_a_dec_trees_6_en = 1'h1;
  assign dec_trees_6_a_dec_trees_6_addr = a_addr_hi[9:7];
  assign dec_trees_6_a_dec_trees_6_data = dec_trees_6[dec_trees_6_a_dec_trees_6_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_6_d_dec_trees_6_en = 1'h1;
  assign dec_trees_6_d_dec_trees_6_addr = d_addr_hi[9:7];
  assign dec_trees_6_d_dec_trees_6_data = dec_trees_6[dec_trees_6_d_dec_trees_6_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_6_MPORT_28_data = wipe ? 2'h0 : _data_T_45;
  assign dec_trees_6_MPORT_28_addr = d_waddr[9:7];
  assign dec_trees_6_MPORT_28_mask = 1'h1;
  assign dec_trees_6_MPORT_28_en = dec_trees_wen[6];
  assign dec_trees_7_a_dec_trees_7_en = 1'h1;
  assign dec_trees_7_a_dec_trees_7_addr = a_addr_hi[9:8];
  assign dec_trees_7_a_dec_trees_7_data = dec_trees_7[dec_trees_7_a_dec_trees_7_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_7_d_dec_trees_7_en = 1'h1;
  assign dec_trees_7_d_dec_trees_7_addr = d_addr_hi[9:8];
  assign dec_trees_7_d_dec_trees_7_data = dec_trees_7[dec_trees_7_d_dec_trees_7_addr]; // @[RAMModel.scala 73:56]
  assign dec_trees_7_MPORT_29_data = wipe ? 2'h0 : _data_T_47;
  assign dec_trees_7_MPORT_29_addr = d_waddr[9:8];
  assign dec_trees_7_MPORT_29_mask = 1'h1;
  assign dec_trees_7_MPORT_29_en = dec_trees_wen[7];
  assign crc_a_crc_acc_MPORT_en = 1'h1;
  assign crc_a_crc_acc_MPORT_addr = a__source;
  assign crc_a_crc_acc_MPORT_data = crc[crc_a_crc_acc_MPORT_addr]; // @[RAMModel.scala 162:20]
  assign crc_d_crc_check_MPORT_en = 1'h1;
  assign crc_d_crc_check_MPORT_addr = d_source;
  assign crc_d_crc_check_MPORT_data = crc[crc_d_crc_check_MPORT_addr]; // @[RAMModel.scala 162:20]
  assign crc_MPORT_data = {a_crc_hi,a_crc_lo};
  assign crc_MPORT_addr = a__source;
  assign crc_MPORT_mask = 1'h1;
  assign crc_MPORT_en = a_fire;
  assign crc_valid_a_crc_valid_MPORT_en = 1'h1;
  assign crc_valid_a_crc_valid_MPORT_addr = a__source;
  assign crc_valid_a_crc_valid_MPORT_data = crc_valid[crc_valid_a_crc_valid_MPORT_addr]; // @[RAMModel.scala 163:26]
  assign crc_valid_d_crc_valid_MPORT_en = 1'h1;
  assign crc_valid_d_crc_valid_MPORT_addr = d_source;
  assign crc_valid_d_crc_valid_MPORT_data = crc_valid[crc_valid_d_crc_valid_MPORT_addr]; // @[RAMModel.scala 163:26]
  assign crc_valid_MPORT_1_data = a_known_old & _a_crc_valid_T;
  assign crc_valid_MPORT_1_addr = a__source;
  assign crc_valid_MPORT_1_mask = 1'h1;
  assign crc_valid_MPORT_1_en = a_fire;
  assign auto_in_a_ready = auto_out_a_ready & ~wipe; // @[RAMModel.scala 51:33]
  assign auto_in_d_valid = auto_out_d_valid & _bundleIn_0_a_ready_T; // @[RAMModel.scala 55:33]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid & _bundleIn_0_a_ready_T; // @[RAMModel.scala 52:33]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = ~wipe; // @[RAMModel.scala 54:36]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready & ~wipe; // @[RAMModel.scala 51:33]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & _bundleIn_0_a_ready_T; // @[RAMModel.scala 55:33]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign alu_io_a_opcode = a__opcode; // @[RAMModel.scala 159:16]
  assign alu_io_a_mask = a__mask; // @[RAMModel.scala 159:16]
  assign alu_io_a_data = a__data; // @[RAMModel.scala 159:16]
  assign alu_io_data_in = {alu_io_data_in_hi,alu_io_data_in_lo}; // @[Cat.scala 33:92]
  always @(posedge clock) begin
    if (shadow_0_valid_MPORT_2_en & shadow_0_valid_MPORT_2_mask) begin
      shadow_0_valid[shadow_0_valid_MPORT_2_addr] <= shadow_0_valid_MPORT_2_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_0_value_MPORT_2_en & shadow_0_value_MPORT_2_mask) begin
      shadow_0_value[shadow_0_value_MPORT_2_addr] <= shadow_0_value_MPORT_2_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_1_valid_MPORT_3_en & shadow_1_valid_MPORT_3_mask) begin
      shadow_1_valid[shadow_1_valid_MPORT_3_addr] <= shadow_1_valid_MPORT_3_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_1_value_MPORT_3_en & shadow_1_value_MPORT_3_mask) begin
      shadow_1_value[shadow_1_value_MPORT_3_addr] <= shadow_1_value_MPORT_3_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_2_valid_MPORT_4_en & shadow_2_valid_MPORT_4_mask) begin
      shadow_2_valid[shadow_2_valid_MPORT_4_addr] <= shadow_2_valid_MPORT_4_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_2_value_MPORT_4_en & shadow_2_value_MPORT_4_mask) begin
      shadow_2_value[shadow_2_value_MPORT_4_addr] <= shadow_2_value_MPORT_4_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_3_valid_MPORT_5_en & shadow_3_valid_MPORT_5_mask) begin
      shadow_3_valid[shadow_3_valid_MPORT_5_addr] <= shadow_3_valid_MPORT_5_data; // @[RAMModel.scala 69:45]
    end
    if (shadow_3_value_MPORT_5_en & shadow_3_value_MPORT_5_mask) begin
      shadow_3_value[shadow_3_value_MPORT_5_addr] <= shadow_3_value_MPORT_5_data; // @[RAMModel.scala 69:45]
    end
    if (inc_bytes_0_MPORT_6_en & inc_bytes_0_MPORT_6_mask) begin
      inc_bytes_0[inc_bytes_0_MPORT_6_addr] <= inc_bytes_0_MPORT_6_data; // @[RAMModel.scala 70:48]
    end
    if (inc_bytes_1_MPORT_7_en & inc_bytes_1_MPORT_7_mask) begin
      inc_bytes_1[inc_bytes_1_MPORT_7_addr] <= inc_bytes_1_MPORT_7_data; // @[RAMModel.scala 70:48]
    end
    if (inc_bytes_2_MPORT_8_en & inc_bytes_2_MPORT_8_mask) begin
      inc_bytes_2[inc_bytes_2_MPORT_8_addr] <= inc_bytes_2_MPORT_8_data; // @[RAMModel.scala 70:48]
    end
    if (inc_bytes_3_MPORT_9_en & inc_bytes_3_MPORT_9_mask) begin
      inc_bytes_3[inc_bytes_3_MPORT_9_addr] <= inc_bytes_3_MPORT_9_data; // @[RAMModel.scala 70:48]
    end
    if (dec_bytes_0_MPORT_18_en & dec_bytes_0_MPORT_18_mask) begin
      dec_bytes_0[dec_bytes_0_MPORT_18_addr] <= dec_bytes_0_MPORT_18_data; // @[RAMModel.scala 71:48]
    end
    if (dec_bytes_1_MPORT_19_en & dec_bytes_1_MPORT_19_mask) begin
      dec_bytes_1[dec_bytes_1_MPORT_19_addr] <= dec_bytes_1_MPORT_19_data; // @[RAMModel.scala 71:48]
    end
    if (dec_bytes_2_MPORT_20_en & dec_bytes_2_MPORT_20_mask) begin
      dec_bytes_2[dec_bytes_2_MPORT_20_addr] <= dec_bytes_2_MPORT_20_data; // @[RAMModel.scala 71:48]
    end
    if (dec_bytes_3_MPORT_21_en & dec_bytes_3_MPORT_21_mask) begin
      dec_bytes_3[dec_bytes_3_MPORT_21_addr] <= dec_bytes_3_MPORT_21_data; // @[RAMModel.scala 71:48]
    end
    if (inc_trees_0_MPORT_10_en & inc_trees_0_MPORT_10_mask) begin
      inc_trees_0[inc_trees_0_MPORT_10_addr] <= inc_trees_0_MPORT_10_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_1_MPORT_11_en & inc_trees_1_MPORT_11_mask) begin
      inc_trees_1[inc_trees_1_MPORT_11_addr] <= inc_trees_1_MPORT_11_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_2_MPORT_12_en & inc_trees_2_MPORT_12_mask) begin
      inc_trees_2[inc_trees_2_MPORT_12_addr] <= inc_trees_2_MPORT_12_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_3_MPORT_13_en & inc_trees_3_MPORT_13_mask) begin
      inc_trees_3[inc_trees_3_MPORT_13_addr] <= inc_trees_3_MPORT_13_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_4_MPORT_14_en & inc_trees_4_MPORT_14_mask) begin
      inc_trees_4[inc_trees_4_MPORT_14_addr] <= inc_trees_4_MPORT_14_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_5_MPORT_15_en & inc_trees_5_MPORT_15_mask) begin
      inc_trees_5[inc_trees_5_MPORT_15_addr] <= inc_trees_5_MPORT_15_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_6_MPORT_16_en & inc_trees_6_MPORT_16_mask) begin
      inc_trees_6[inc_trees_6_MPORT_16_addr] <= inc_trees_6_MPORT_16_data; // @[RAMModel.scala 72:56]
    end
    if (inc_trees_7_MPORT_17_en & inc_trees_7_MPORT_17_mask) begin
      inc_trees_7[inc_trees_7_MPORT_17_addr] <= inc_trees_7_MPORT_17_data; // @[RAMModel.scala 72:56]
    end
    if (dec_trees_0_MPORT_22_en & dec_trees_0_MPORT_22_mask) begin
      dec_trees_0[dec_trees_0_MPORT_22_addr] <= dec_trees_0_MPORT_22_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_1_MPORT_23_en & dec_trees_1_MPORT_23_mask) begin
      dec_trees_1[dec_trees_1_MPORT_23_addr] <= dec_trees_1_MPORT_23_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_2_MPORT_24_en & dec_trees_2_MPORT_24_mask) begin
      dec_trees_2[dec_trees_2_MPORT_24_addr] <= dec_trees_2_MPORT_24_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_3_MPORT_25_en & dec_trees_3_MPORT_25_mask) begin
      dec_trees_3[dec_trees_3_MPORT_25_addr] <= dec_trees_3_MPORT_25_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_4_MPORT_26_en & dec_trees_4_MPORT_26_mask) begin
      dec_trees_4[dec_trees_4_MPORT_26_addr] <= dec_trees_4_MPORT_26_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_5_MPORT_27_en & dec_trees_5_MPORT_27_mask) begin
      dec_trees_5[dec_trees_5_MPORT_27_addr] <= dec_trees_5_MPORT_27_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_6_MPORT_28_en & dec_trees_6_MPORT_28_mask) begin
      dec_trees_6[dec_trees_6_MPORT_28_addr] <= dec_trees_6_MPORT_28_data; // @[RAMModel.scala 73:56]
    end
    if (dec_trees_7_MPORT_29_en & dec_trees_7_MPORT_29_mask) begin
      dec_trees_7[dec_trees_7_MPORT_29_addr] <= dec_trees_7_MPORT_29_data; // @[RAMModel.scala 73:56]
    end
    if (crc_MPORT_en & crc_MPORT_mask) begin
      crc[crc_MPORT_addr] <= crc_MPORT_data; // @[RAMModel.scala 162:20]
    end
    if (crc_valid_MPORT_1_en & crc_valid_MPORT_1_mask) begin
      crc_valid[crc_valid_MPORT_1_addr] <= crc_valid_MPORT_1_data; // @[RAMModel.scala 163:26]
    end
    if (reset) begin // @[RAMModel.scala 46:30]
      wipeIndex <= 11'h0; // @[RAMModel.scala 46:30]
    end else begin
      wipeIndex <= _wipeIndex_T_1; // @[RAMModel.scala 48:17]
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h0 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_0_base <= auto_in_a_bits_address; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h0 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_0_size <= auto_in_a_bits_size; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h0 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_0_opcode <= auto_in_a_bits_opcode; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h1 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_1_base <= auto_in_a_bits_address; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h1 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_1_size <= auto_in_a_bits_size; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h1 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_1_opcode <= auto_in_a_bits_opcode; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h2 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_2_base <= auto_in_a_bits_address; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h2 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_2_size <= auto_in_a_bits_size; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h2 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_2_opcode <= auto_in_a_bits_opcode; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h3 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_3_base <= auto_in_a_bits_address; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h3 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_3_size <= auto_in_a_bits_size; // @[RAMModel.scala 91:53]
      end
    end
    if (_T) begin // @[RAMModel.scala 91:26]
      if (2'h3 == auto_in_a_bits_source) begin // @[RAMModel.scala 91:53]
        flight_3_opcode <= auto_in_a_bits_opcode; // @[RAMModel.scala 91:53]
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_flight_counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (_d_flight_T_1) begin // @[Edges.scala 234:17]
      if (d_flight_first) begin // @[Edges.scala 235:21]
        if (d_flight_beats1_opdata) begin // @[Edges.scala 220:14]
          d_flight_counter <= d_flight_beats1_decode;
        end else begin
          d_flight_counter <= 8'h0;
        end
      end else begin
        d_flight_counter <= d_flight_counter1;
      end
    end
    if (d_flight_first) begin // @[Reg.scala 20:18]
      if (2'h3 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_base <= flight_3_base; // @[RAMModel.scala 93:35]
      end else if (2'h2 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_base <= flight_2_base; // @[RAMModel.scala 93:35]
      end else if (2'h1 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_base <= flight_1_base; // @[RAMModel.scala 93:35]
      end else begin
        d_flight_base <= flight_0_base;
      end
    end
    if (d_flight_first) begin // @[Reg.scala 20:18]
      if (2'h3 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_size <= flight_3_size; // @[RAMModel.scala 93:35]
      end else if (2'h2 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_size <= flight_2_size; // @[RAMModel.scala 93:35]
      end else if (2'h1 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_size <= flight_1_size; // @[RAMModel.scala 93:35]
      end else begin
        d_flight_size <= flight_0_size;
      end
    end
    if (d_flight_first) begin // @[Reg.scala 20:18]
      if (2'h3 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_opcode <= flight_3_opcode; // @[RAMModel.scala 93:35]
      end else if (2'h2 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_opcode <= flight_2_opcode; // @[RAMModel.scala 93:35]
      end else if (2'h1 == auto_out_d_bits_source) begin // @[RAMModel.scala 93:35]
        d_flight_opcode <= flight_1_opcode; // @[RAMModel.scala 93:35]
      end else begin
        d_flight_opcode <= flight_0_opcode;
      end
    end
    a__opcode <= auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__size <= auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__source <= auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__address <= auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__mask <= auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    a__data <= auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
    if (reset) begin // @[RAMModel.scala 97:23]
      a_fire <= 1'h0; // @[RAMModel.scala 97:23]
    end else begin
      a_fire <= _T; // @[RAMModel.scala 97:23]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 8'h0; // @[Edges.scala 228:27]
    end else if (a_fire) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 8'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    d_opcode <= auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    d_size <= auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    d_source <= auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    d_denied <= auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    d_data <= auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
    if (reset) begin // @[RAMModel.scala 201:23]
      d_fire <= 1'h0; // @[RAMModel.scala 201:23]
    end else begin
      d_fire <= _d_flight_T_1; // @[RAMModel.scala 201:23]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter_1 <= 8'h0; // @[Edges.scala 228:27]
    end else if (d_fire) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata_1) begin // @[Edges.scala 220:14]
          counter_1 <= beats1_decode_1;
        end else begin
          counter_1 <= 8'h0;
        end
      end else begin
        counter_1 <= counter1_1;
      end
    end
    if (d_fire) begin // @[RAMModel.scala 235:21]
      d_crc_reg <= d_crc; // @[RAMModel.scala 236:19]
    end
    if (d_first) begin // @[Reg.scala 20:18]
      d_crc_valid_r <= _d_crc_valid_T; // @[Reg.scala 20:22]
    end
    if (d_first) begin // @[Reg.scala 20:18]
      d_crc_check_r <= _d_crc_check_T; // @[Reg.scala 20:22]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & ~reset & ~(a__opcode != 3'h6 & a__opcode != 3'h7)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RAMModel.scala:119 assert (a.opcode =/= TLMessages.AcquireBlock && a.opcode =/= TLMessages.AcquirePerm)\n"
            ); // @[RAMModel.scala 119:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(a__opcode != 3'h6 & a__opcode != 3'h7) & (a_fire & ~reset)) begin
          $fatal; // @[RAMModel.scala 119:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_18 & a__mask[0] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 139:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_12 & _T_5) begin
          $fwrite(32'h80000002,"PF"); // @[RAMModel.scala 140:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_13 & _T_5) begin
          $fwrite(32'h80000002,"PP"); // @[RAMModel.scala 141:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_15 & _T_5) begin
          $fwrite(32'h80000002,"A "); // @[RAMModel.scala 142:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_17 & _T_5) begin
          $fwrite(32'h80000002,"L "); // @[RAMModel.scala 143:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_256 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x #%d %x\n",{a_addr_hi, 2'h0},byte_,busy,3'h0); // @[RAMModel.scala 144:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_18 & a__mask[1] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 139:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_12 & _T_5) begin
          $fwrite(32'h80000002,"PF"); // @[RAMModel.scala 140:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_13 & _T_5) begin
          $fwrite(32'h80000002,"PP"); // @[RAMModel.scala 141:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_15 & _T_5) begin
          $fwrite(32'h80000002,"A "); // @[RAMModel.scala 142:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_17 & _T_5) begin
          $fwrite(32'h80000002,"L "); // @[RAMModel.scala 143:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_272 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x #%d %x\n",_T_34 | 12'h1,byte_1,busy_1,3'h0); // @[RAMModel.scala 144:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_18 & a__mask[2] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 139:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_12 & _T_5) begin
          $fwrite(32'h80000002,"PF"); // @[RAMModel.scala 140:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_13 & _T_5) begin
          $fwrite(32'h80000002,"PP"); // @[RAMModel.scala 141:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_15 & _T_5) begin
          $fwrite(32'h80000002,"A "); // @[RAMModel.scala 142:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_17 & _T_5) begin
          $fwrite(32'h80000002,"L "); // @[RAMModel.scala 143:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_288 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x #%d %x\n",_T_34 | 12'h2,byte_2,busy_2,3'h0); // @[RAMModel.scala 144:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_18 & a__mask[3] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 139:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_12 & _T_5) begin
          $fwrite(32'h80000002,"PF"); // @[RAMModel.scala 140:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_13 & _T_5) begin
          $fwrite(32'h80000002,"PP"); // @[RAMModel.scala 141:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_15 & _T_5) begin
          $fwrite(32'h80000002,"A "); // @[RAMModel.scala 142:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_17 & _T_5) begin
          $fwrite(32'h80000002,"L "); // @[RAMModel.scala 143:66]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_304 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x #%d %x\n",_T_34 | 12'h3,byte_3,busy_3,3'h0); // @[RAMModel.scala 144:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (a_fire & _T_95 & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 G  0x%x - 0x%x\n",a__address,a__address | _T_99); // @[RAMModel.scala 150:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_5 & ~(d_size == d_flight_size)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:240 assert (d_size === d_flight.size)\n"); // @[RAMModel.scala 240:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_size == d_flight_size) & (d_fire & _T_5)) begin
          $fatal; // @[RAMModel.scala 240:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_147 & _T_5 & ~(d_opcode == 3'h2)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:244 assert (d.opcode === TLMessages.HintAck)\n"
            ); // @[RAMModel.scala 244:18]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_opcode == 3'h2) & (d_fire & _T_147 & _T_5)) begin
          $fatal; // @[RAMModel.scala 244:18]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_159 & _T_5 & ~(d_opcode == 3'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RAMModel.scala:266 assert (d.opcode === TLMessages.AccessAck)\n"); // @[RAMModel.scala 266:18]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_opcode == 3'h0) & (d_fire & _T_159 & _T_5)) begin
          $fatal; // @[RAMModel.scala 266:18]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_328 & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 267:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_328 & _T_157 & _T_5) begin
          $fwrite(32'h80000002,"pf"); // @[RAMModel.scala 268:69]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_328 & _T_158 & _T_5) begin
          $fwrite(32'h80000002,"pp"); // @[RAMModel.scala 269:72]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_328 & _T_5) begin
          $fwrite(32'h80000002," 0x%x - 0x%x\n",d_flight_base,d_flight_base | d_bits); // @[RAMModel.scala 270:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_183 & _T_5 & ~(d_opcode == 3'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RAMModel.scala:274 assert (d.opcode === TLMessages.AccessAckData)\n"); // @[RAMModel.scala 274:18]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_opcode == 3'h1) & (d_fire & _T_183 & _T_5)) begin
          $fatal; // @[RAMModel.scala 274:18]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_339 & d_mask[0] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 280:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_179 & _T_5) begin
          $fwrite(32'h80000002,"g "); // @[RAMModel.scala 281:65]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_180 & _T_5) begin
          $fwrite(32'h80000002,"a "); // @[RAMModel.scala 282:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_182 & _T_5) begin
          $fwrite(32'h80000002,"l "); // @[RAMModel.scala 283:73]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x",d_addr,got); // @[RAMModel.scala 284:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & _T_202 & _T_5) begin
          $fwrite(32'h80000002,", undefined (uninitialized or prior overlapping puts)\n"); // @[RAMModel.scala 286:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_345 & ~_T_202 & _T_205 & _T_5) begin
          $fwrite(32'h80000002,", undefined (concurrent incomplete puts #%d)\n",d_inc_0 - d_dec_0); // @[RAMModel.scala 288:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_363 & ~_T_205 & d_denied & _T_5) begin
          $fwrite(32'h80000002,", undefined (denied result)\n"); // @[RAMModel.scala 292:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_370 & _T_364 & _T_5) begin
          $fwrite(32'h80000002,"\n"); // @[RAMModel.scala 296:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_379 & shadow_value != got & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",shadow_value); // @[RAMModel.scala 297:53]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_379 & _T_5 & ~(shadow_value == got)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:298 assert (shadow.value === got)\n"); // @[RAMModel.scala 298:24]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(shadow_value == got) & (_GEN_379 & _T_5)) begin
          $fatal; // @[RAMModel.scala 298:24]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_339 & d_mask[1] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 280:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_179 & _T_5) begin
          $fwrite(32'h80000002,"g "); // @[RAMModel.scala 281:65]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_180 & _T_5) begin
          $fwrite(32'h80000002,"a "); // @[RAMModel.scala 282:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_182 & _T_5) begin
          $fwrite(32'h80000002,"l "); // @[RAMModel.scala 283:73]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x",d_addr_1,got_1); // @[RAMModel.scala 284:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & _T_244 & _T_5) begin
          $fwrite(32'h80000002,", undefined (uninitialized or prior overlapping puts)\n"); // @[RAMModel.scala 286:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_409 & ~_T_244 & _T_247 & _T_5) begin
          $fwrite(32'h80000002,", undefined (concurrent incomplete puts #%d)\n",d_inc_1 - d_dec_1); // @[RAMModel.scala 288:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_427 & ~_T_247 & d_denied & _T_5) begin
          $fwrite(32'h80000002,", undefined (denied result)\n"); // @[RAMModel.scala 292:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_434 & _T_364 & _T_5) begin
          $fwrite(32'h80000002,"\n"); // @[RAMModel.scala 296:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_443 & shadow_4_value != got_1 & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",shadow_4_value); // @[RAMModel.scala 297:53]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_443 & _T_5 & ~(shadow_4_value == got_1)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:298 assert (shadow.value === got)\n"); // @[RAMModel.scala 298:24]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(shadow_4_value == got_1) & (_GEN_443 & _T_5)) begin
          $fatal; // @[RAMModel.scala 298:24]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_339 & d_mask[2] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 280:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_179 & _T_5) begin
          $fwrite(32'h80000002,"g "); // @[RAMModel.scala 281:65]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_180 & _T_5) begin
          $fwrite(32'h80000002,"a "); // @[RAMModel.scala 282:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_182 & _T_5) begin
          $fwrite(32'h80000002,"l "); // @[RAMModel.scala 283:73]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x",d_addr_2,got_2); // @[RAMModel.scala 284:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & _T_286 & _T_5) begin
          $fwrite(32'h80000002,", undefined (uninitialized or prior overlapping puts)\n"); // @[RAMModel.scala 286:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_473 & ~_T_286 & _T_289 & _T_5) begin
          $fwrite(32'h80000002,", undefined (concurrent incomplete puts #%d)\n",d_inc_2 - d_dec_2); // @[RAMModel.scala 288:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_491 & ~_T_289 & d_denied & _T_5) begin
          $fwrite(32'h80000002,", undefined (denied result)\n"); // @[RAMModel.scala 292:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_498 & _T_364 & _T_5) begin
          $fwrite(32'h80000002,"\n"); // @[RAMModel.scala 296:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_507 & shadow_5_value != got_2 & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",shadow_5_value); // @[RAMModel.scala 297:53]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_507 & _T_5 & ~(shadow_5_value == got_2)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:298 assert (shadow.value === got)\n"); // @[RAMModel.scala 298:24]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(shadow_5_value == got_2) & (_GEN_507 & _T_5)) begin
          $fatal; // @[RAMModel.scala 298:24]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_339 & d_mask[3] & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 "); // @[RAMModel.scala 280:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_179 & _T_5) begin
          $fwrite(32'h80000002,"g "); // @[RAMModel.scala 281:65]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_180 & _T_5) begin
          $fwrite(32'h80000002,"a "); // @[RAMModel.scala 282:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_182 & _T_5) begin
          $fwrite(32'h80000002,"l "); // @[RAMModel.scala 283:73]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_5) begin
          $fwrite(32'h80000002," 0x%x := 0x%x",d_addr_3,got_3); // @[RAMModel.scala 284:21]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & _T_328 & _T_5) begin
          $fwrite(32'h80000002,", undefined (uninitialized or prior overlapping puts)\n"); // @[RAMModel.scala 286:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_537 & ~_T_328 & _T_331 & _T_5) begin
          $fwrite(32'h80000002,", undefined (concurrent incomplete puts #%d)\n",d_inc_3 - d_dec_3); // @[RAMModel.scala 288:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_555 & ~_T_331 & d_denied & _T_5) begin
          $fwrite(32'h80000002,", undefined (denied result)\n"); // @[RAMModel.scala 292:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_562 & _T_364 & _T_5) begin
          $fwrite(32'h80000002,"\n"); // @[RAMModel.scala 296:23]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_571 & shadow_6_value != got_3 & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",shadow_6_value); // @[RAMModel.scala 297:53]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_571 & _T_5 & ~(shadow_6_value == got_3)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at RAMModel.scala:298 assert (shadow.value === got)\n"); // @[RAMModel.scala 298:24]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(shadow_6_value == got_3) & (_GEN_571 & _T_5)) begin
          $fatal; // @[RAMModel.scala 298:24]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (d_fire & _T_358 & d_last & _T_5) begin
          $fwrite(32'h80000002,"XBar2to1 Master 1 crc = 0x%x %d\n",d_crc,_GEN_152); // @[RAMModel.scala 311:19]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_601 & (~d_denied & _GEN_152 & d_crc != _GEN_153) & _T_5) begin
          $fwrite(32'h80000002,"EXPECTED: 0x%x\n",_GEN_153); // @[RAMModel.scala 312:76]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_601 & _T_5 & ~(d_denied | ~_GEN_152 | d_crc == _GEN_153)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RAMModel.scala:313 assert (corrupt || !must_match || d_crc === d_crc_check)\n"); // @[RAMModel.scala 313:20]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(d_denied | ~_GEN_152 | d_crc == _GEN_153) & (_GEN_601 & _T_5)) begin
          $fatal; // @[RAMModel.scala 313:20]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    shadow_0_valid[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    shadow_0_value[initvar] = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    shadow_1_valid[initvar] = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    shadow_1_value[initvar] = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    shadow_2_valid[initvar] = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    shadow_2_value[initvar] = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    shadow_3_valid[initvar] = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    shadow_3_value[initvar] = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    inc_bytes_0[initvar] = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    inc_bytes_1[initvar] = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    inc_bytes_2[initvar] = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    inc_bytes_3[initvar] = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    dec_bytes_0[initvar] = _RAND_12[1:0];
  _RAND_13 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    dec_bytes_1[initvar] = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    dec_bytes_2[initvar] = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1024; initvar = initvar+1)
    dec_bytes_3[initvar] = _RAND_15[1:0];
  _RAND_16 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    inc_trees_0[initvar] = _RAND_16[1:0];
  _RAND_17 = {1{`RANDOM}};
  for (initvar = 0; initvar < 256; initvar = initvar+1)
    inc_trees_1[initvar] = _RAND_17[1:0];
  _RAND_18 = {1{`RANDOM}};
  for (initvar = 0; initvar < 128; initvar = initvar+1)
    inc_trees_2[initvar] = _RAND_18[1:0];
  _RAND_19 = {1{`RANDOM}};
  for (initvar = 0; initvar < 64; initvar = initvar+1)
    inc_trees_3[initvar] = _RAND_19[1:0];
  _RAND_20 = {1{`RANDOM}};
  for (initvar = 0; initvar < 32; initvar = initvar+1)
    inc_trees_4[initvar] = _RAND_20[1:0];
  _RAND_21 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    inc_trees_5[initvar] = _RAND_21[1:0];
  _RAND_22 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    inc_trees_6[initvar] = _RAND_22[1:0];
  _RAND_23 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    inc_trees_7[initvar] = _RAND_23[1:0];
  _RAND_24 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    dec_trees_0[initvar] = _RAND_24[1:0];
  _RAND_25 = {1{`RANDOM}};
  for (initvar = 0; initvar < 256; initvar = initvar+1)
    dec_trees_1[initvar] = _RAND_25[1:0];
  _RAND_26 = {1{`RANDOM}};
  for (initvar = 0; initvar < 128; initvar = initvar+1)
    dec_trees_2[initvar] = _RAND_26[1:0];
  _RAND_27 = {1{`RANDOM}};
  for (initvar = 0; initvar < 64; initvar = initvar+1)
    dec_trees_3[initvar] = _RAND_27[1:0];
  _RAND_28 = {1{`RANDOM}};
  for (initvar = 0; initvar < 32; initvar = initvar+1)
    dec_trees_4[initvar] = _RAND_28[1:0];
  _RAND_29 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    dec_trees_5[initvar] = _RAND_29[1:0];
  _RAND_30 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    dec_trees_6[initvar] = _RAND_30[1:0];
  _RAND_31 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    dec_trees_7[initvar] = _RAND_31[1:0];
  _RAND_32 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    crc[initvar] = _RAND_32[15:0];
  _RAND_33 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    crc_valid[initvar] = _RAND_33[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_34 = {1{`RANDOM}};
  wipeIndex = _RAND_34[10:0];
  _RAND_35 = {1{`RANDOM}};
  flight_0_base = _RAND_35[11:0];
  _RAND_36 = {1{`RANDOM}};
  flight_0_size = _RAND_36[3:0];
  _RAND_37 = {1{`RANDOM}};
  flight_0_opcode = _RAND_37[2:0];
  _RAND_38 = {1{`RANDOM}};
  flight_1_base = _RAND_38[11:0];
  _RAND_39 = {1{`RANDOM}};
  flight_1_size = _RAND_39[3:0];
  _RAND_40 = {1{`RANDOM}};
  flight_1_opcode = _RAND_40[2:0];
  _RAND_41 = {1{`RANDOM}};
  flight_2_base = _RAND_41[11:0];
  _RAND_42 = {1{`RANDOM}};
  flight_2_size = _RAND_42[3:0];
  _RAND_43 = {1{`RANDOM}};
  flight_2_opcode = _RAND_43[2:0];
  _RAND_44 = {1{`RANDOM}};
  flight_3_base = _RAND_44[11:0];
  _RAND_45 = {1{`RANDOM}};
  flight_3_size = _RAND_45[3:0];
  _RAND_46 = {1{`RANDOM}};
  flight_3_opcode = _RAND_46[2:0];
  _RAND_47 = {1{`RANDOM}};
  d_flight_counter = _RAND_47[7:0];
  _RAND_48 = {1{`RANDOM}};
  d_flight_base = _RAND_48[11:0];
  _RAND_49 = {1{`RANDOM}};
  d_flight_size = _RAND_49[3:0];
  _RAND_50 = {1{`RANDOM}};
  d_flight_opcode = _RAND_50[2:0];
  _RAND_51 = {1{`RANDOM}};
  a__opcode = _RAND_51[2:0];
  _RAND_52 = {1{`RANDOM}};
  a__size = _RAND_52[3:0];
  _RAND_53 = {1{`RANDOM}};
  a__source = _RAND_53[1:0];
  _RAND_54 = {1{`RANDOM}};
  a__address = _RAND_54[11:0];
  _RAND_55 = {1{`RANDOM}};
  a__mask = _RAND_55[3:0];
  _RAND_56 = {1{`RANDOM}};
  a__data = _RAND_56[31:0];
  _RAND_57 = {1{`RANDOM}};
  a_fire = _RAND_57[0:0];
  _RAND_58 = {1{`RANDOM}};
  counter = _RAND_58[7:0];
  _RAND_59 = {1{`RANDOM}};
  d_opcode = _RAND_59[2:0];
  _RAND_60 = {1{`RANDOM}};
  d_size = _RAND_60[3:0];
  _RAND_61 = {1{`RANDOM}};
  d_source = _RAND_61[1:0];
  _RAND_62 = {1{`RANDOM}};
  d_denied = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  d_data = _RAND_63[31:0];
  _RAND_64 = {1{`RANDOM}};
  d_fire = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  counter_1 = _RAND_65[7:0];
  _RAND_66 = {1{`RANDOM}};
  d_crc_reg = _RAND_66[15:0];
  _RAND_67 = {1{`RANDOM}};
  d_crc_valid_r = _RAND_67[0:0];
  _RAND_68 = {1{`RANDOM}};
  d_crc_check_r = _RAND_68[15:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module myAXI4XbarFuzzTest(
  input   clock,
  input   reset,
  output  io_finished,
  input   io_start
);
  wire  axi4xbar_clock; // @[Xbar.scala 218:30]
  wire  axi4xbar_reset; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_aw_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_aw_valid; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_aw_bits_id; // @[Xbar.scala 218:30]
  wire [11:0] axi4xbar_auto_in_1_aw_bits_addr; // @[Xbar.scala 218:30]
  wire [7:0] axi4xbar_auto_in_1_aw_bits_len; // @[Xbar.scala 218:30]
  wire [2:0] axi4xbar_auto_in_1_aw_bits_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_1_aw_bits_burst; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_1_aw_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_1_aw_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_w_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_w_valid; // @[Xbar.scala 218:30]
  wire [31:0] axi4xbar_auto_in_1_w_bits_data; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_1_w_bits_strb; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_w_bits_last; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_b_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_b_valid; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_1_b_bits_resp; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_1_b_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_1_b_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_ar_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_ar_valid; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_ar_bits_id; // @[Xbar.scala 218:30]
  wire [11:0] axi4xbar_auto_in_1_ar_bits_addr; // @[Xbar.scala 218:30]
  wire [7:0] axi4xbar_auto_in_1_ar_bits_len; // @[Xbar.scala 218:30]
  wire [2:0] axi4xbar_auto_in_1_ar_bits_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_1_ar_bits_burst; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_1_ar_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_1_ar_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_r_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_r_valid; // @[Xbar.scala 218:30]
  wire [31:0] axi4xbar_auto_in_1_r_bits_data; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_1_r_bits_resp; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_1_r_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_1_r_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_1_r_bits_last; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_aw_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_aw_valid; // @[Xbar.scala 218:30]
  wire [11:0] axi4xbar_auto_in_0_aw_bits_addr; // @[Xbar.scala 218:30]
  wire [7:0] axi4xbar_auto_in_0_aw_bits_len; // @[Xbar.scala 218:30]
  wire [2:0] axi4xbar_auto_in_0_aw_bits_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_0_aw_bits_burst; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_0_aw_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_0_aw_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_w_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_w_valid; // @[Xbar.scala 218:30]
  wire [31:0] axi4xbar_auto_in_0_w_bits_data; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_0_w_bits_strb; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_w_bits_last; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_b_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_b_valid; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_0_b_bits_resp; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_0_b_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_0_b_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_ar_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_ar_valid; // @[Xbar.scala 218:30]
  wire [11:0] axi4xbar_auto_in_0_ar_bits_addr; // @[Xbar.scala 218:30]
  wire [7:0] axi4xbar_auto_in_0_ar_bits_len; // @[Xbar.scala 218:30]
  wire [2:0] axi4xbar_auto_in_0_ar_bits_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_0_ar_bits_burst; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_0_ar_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_0_ar_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_r_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_r_valid; // @[Xbar.scala 218:30]
  wire [31:0] axi4xbar_auto_in_0_r_bits_data; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_0_r_bits_resp; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_in_0_r_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_in_0_r_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_in_0_r_bits_last; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_aw_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_aw_valid; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_aw_bits_id; // @[Xbar.scala 218:30]
  wire [11:0] axi4xbar_auto_out_aw_bits_addr; // @[Xbar.scala 218:30]
  wire [7:0] axi4xbar_auto_out_aw_bits_len; // @[Xbar.scala 218:30]
  wire [2:0] axi4xbar_auto_out_aw_bits_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_out_aw_bits_burst; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_out_aw_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_out_aw_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_w_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_w_valid; // @[Xbar.scala 218:30]
  wire [31:0] axi4xbar_auto_out_w_bits_data; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_out_w_bits_strb; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_w_bits_last; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_b_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_b_valid; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_b_bits_id; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_out_b_bits_resp; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_out_b_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_out_b_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_ar_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_ar_valid; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_ar_bits_id; // @[Xbar.scala 218:30]
  wire [11:0] axi4xbar_auto_out_ar_bits_addr; // @[Xbar.scala 218:30]
  wire [7:0] axi4xbar_auto_out_ar_bits_len; // @[Xbar.scala 218:30]
  wire [2:0] axi4xbar_auto_out_ar_bits_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_out_ar_bits_burst; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_out_ar_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_out_ar_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_r_ready; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_r_valid; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_r_bits_id; // @[Xbar.scala 218:30]
  wire [31:0] axi4xbar_auto_out_r_bits_data; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_out_r_bits_resp; // @[Xbar.scala 218:30]
  wire [3:0] axi4xbar_auto_out_r_bits_echo_tl_state_size; // @[Xbar.scala 218:30]
  wire [1:0] axi4xbar_auto_out_r_bits_echo_tl_state_source; // @[Xbar.scala 218:30]
  wire  axi4xbar_auto_out_r_bits_last; // @[Xbar.scala 218:30]
  wire  slaves_clock; // @[Xbar.scala 298:55]
  wire  slaves_reset; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_aw_ready; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_aw_valid; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_aw_bits_id; // @[Xbar.scala 298:55]
  wire [11:0] slaves_auto_in_aw_bits_addr; // @[Xbar.scala 298:55]
  wire [3:0] slaves_auto_in_aw_bits_echo_tl_state_size; // @[Xbar.scala 298:55]
  wire [1:0] slaves_auto_in_aw_bits_echo_tl_state_source; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_aw_bits_echo_real_last; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_w_ready; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_w_valid; // @[Xbar.scala 298:55]
  wire [31:0] slaves_auto_in_w_bits_data; // @[Xbar.scala 298:55]
  wire [3:0] slaves_auto_in_w_bits_strb; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_b_ready; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_b_valid; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_b_bits_id; // @[Xbar.scala 298:55]
  wire [1:0] slaves_auto_in_b_bits_resp; // @[Xbar.scala 298:55]
  wire [3:0] slaves_auto_in_b_bits_echo_tl_state_size; // @[Xbar.scala 298:55]
  wire [1:0] slaves_auto_in_b_bits_echo_tl_state_source; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_b_bits_echo_real_last; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_ar_ready; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_ar_valid; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_ar_bits_id; // @[Xbar.scala 298:55]
  wire [11:0] slaves_auto_in_ar_bits_addr; // @[Xbar.scala 298:55]
  wire [3:0] slaves_auto_in_ar_bits_echo_tl_state_size; // @[Xbar.scala 298:55]
  wire [1:0] slaves_auto_in_ar_bits_echo_tl_state_source; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_ar_bits_echo_real_last; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_r_ready; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_r_valid; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_r_bits_id; // @[Xbar.scala 298:55]
  wire [31:0] slaves_auto_in_r_bits_data; // @[Xbar.scala 298:55]
  wire [1:0] slaves_auto_in_r_bits_resp; // @[Xbar.scala 298:55]
  wire [3:0] slaves_auto_in_r_bits_echo_tl_state_size; // @[Xbar.scala 298:55]
  wire [1:0] slaves_auto_in_r_bits_echo_tl_state_source; // @[Xbar.scala 298:55]
  wire  slaves_auto_in_r_bits_echo_real_last; // @[Xbar.scala 298:55]
  wire  axi4frag_clock; // @[Fragmenter.scala 205:30]
  wire  axi4frag_reset; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_aw_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_aw_valid; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_aw_bits_id; // @[Fragmenter.scala 205:30]
  wire [11:0] axi4frag_auto_in_aw_bits_addr; // @[Fragmenter.scala 205:30]
  wire [7:0] axi4frag_auto_in_aw_bits_len; // @[Fragmenter.scala 205:30]
  wire [2:0] axi4frag_auto_in_aw_bits_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_in_aw_bits_burst; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_in_aw_bits_echo_tl_state_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_in_aw_bits_echo_tl_state_source; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_w_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_w_valid; // @[Fragmenter.scala 205:30]
  wire [31:0] axi4frag_auto_in_w_bits_data; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_in_w_bits_strb; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_w_bits_last; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_b_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_b_valid; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_b_bits_id; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_in_b_bits_resp; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_in_b_bits_echo_tl_state_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_in_b_bits_echo_tl_state_source; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_ar_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_ar_valid; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_ar_bits_id; // @[Fragmenter.scala 205:30]
  wire [11:0] axi4frag_auto_in_ar_bits_addr; // @[Fragmenter.scala 205:30]
  wire [7:0] axi4frag_auto_in_ar_bits_len; // @[Fragmenter.scala 205:30]
  wire [2:0] axi4frag_auto_in_ar_bits_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_in_ar_bits_burst; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_in_ar_bits_echo_tl_state_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_in_ar_bits_echo_tl_state_source; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_r_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_r_valid; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_r_bits_id; // @[Fragmenter.scala 205:30]
  wire [31:0] axi4frag_auto_in_r_bits_data; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_in_r_bits_resp; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_in_r_bits_echo_tl_state_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_in_r_bits_echo_tl_state_source; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_in_r_bits_last; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_aw_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_aw_valid; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_aw_bits_id; // @[Fragmenter.scala 205:30]
  wire [11:0] axi4frag_auto_out_aw_bits_addr; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_out_aw_bits_echo_tl_state_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_out_aw_bits_echo_tl_state_source; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_aw_bits_echo_real_last; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_w_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_w_valid; // @[Fragmenter.scala 205:30]
  wire [31:0] axi4frag_auto_out_w_bits_data; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_out_w_bits_strb; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_b_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_b_valid; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_b_bits_id; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_out_b_bits_resp; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_out_b_bits_echo_tl_state_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_out_b_bits_echo_tl_state_source; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_b_bits_echo_real_last; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_ar_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_ar_valid; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_ar_bits_id; // @[Fragmenter.scala 205:30]
  wire [11:0] axi4frag_auto_out_ar_bits_addr; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_out_ar_bits_echo_tl_state_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_out_ar_bits_echo_tl_state_source; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_ar_bits_echo_real_last; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_r_ready; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_r_valid; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_r_bits_id; // @[Fragmenter.scala 205:30]
  wire [31:0] axi4frag_auto_out_r_bits_data; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_out_r_bits_resp; // @[Fragmenter.scala 205:30]
  wire [3:0] axi4frag_auto_out_r_bits_echo_tl_state_size; // @[Fragmenter.scala 205:30]
  wire [1:0] axi4frag_auto_out_r_bits_echo_tl_state_source; // @[Fragmenter.scala 205:30]
  wire  axi4frag_auto_out_r_bits_echo_real_last; // @[Fragmenter.scala 205:30]
  wire  axi4buf_clock; // @[Buffer.scala 58:29]
  wire  axi4buf_reset; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_aw_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_aw_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_aw_bits_id; // @[Buffer.scala 58:29]
  wire [11:0] axi4buf_auto_in_aw_bits_addr; // @[Buffer.scala 58:29]
  wire [7:0] axi4buf_auto_in_aw_bits_len; // @[Buffer.scala 58:29]
  wire [2:0] axi4buf_auto_in_aw_bits_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_in_aw_bits_burst; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_in_aw_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_in_aw_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_w_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_w_valid; // @[Buffer.scala 58:29]
  wire [31:0] axi4buf_auto_in_w_bits_data; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_in_w_bits_strb; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_w_bits_last; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_b_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_b_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_b_bits_id; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_in_b_bits_resp; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_in_b_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_in_b_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_ar_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_ar_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_ar_bits_id; // @[Buffer.scala 58:29]
  wire [11:0] axi4buf_auto_in_ar_bits_addr; // @[Buffer.scala 58:29]
  wire [7:0] axi4buf_auto_in_ar_bits_len; // @[Buffer.scala 58:29]
  wire [2:0] axi4buf_auto_in_ar_bits_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_in_ar_bits_burst; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_in_ar_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_in_ar_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_r_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_r_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_r_bits_id; // @[Buffer.scala 58:29]
  wire [31:0] axi4buf_auto_in_r_bits_data; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_in_r_bits_resp; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_in_r_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_in_r_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_in_r_bits_last; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_aw_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_aw_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_aw_bits_id; // @[Buffer.scala 58:29]
  wire [11:0] axi4buf_auto_out_aw_bits_addr; // @[Buffer.scala 58:29]
  wire [7:0] axi4buf_auto_out_aw_bits_len; // @[Buffer.scala 58:29]
  wire [2:0] axi4buf_auto_out_aw_bits_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_out_aw_bits_burst; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_out_aw_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_out_aw_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_w_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_w_valid; // @[Buffer.scala 58:29]
  wire [31:0] axi4buf_auto_out_w_bits_data; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_out_w_bits_strb; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_w_bits_last; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_b_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_b_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_b_bits_id; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_out_b_bits_resp; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_out_b_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_out_b_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_ar_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_ar_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_ar_bits_id; // @[Buffer.scala 58:29]
  wire [11:0] axi4buf_auto_out_ar_bits_addr; // @[Buffer.scala 58:29]
  wire [7:0] axi4buf_auto_out_ar_bits_len; // @[Buffer.scala 58:29]
  wire [2:0] axi4buf_auto_out_ar_bits_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_out_ar_bits_burst; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_out_ar_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_out_ar_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_r_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_r_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_r_bits_id; // @[Buffer.scala 58:29]
  wire [31:0] axi4buf_auto_out_r_bits_data; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_out_r_bits_resp; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_auto_out_r_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_auto_out_r_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_auto_out_r_bits_last; // @[Buffer.scala 58:29]
  wire  axi4buf_1_clock; // @[Buffer.scala 58:29]
  wire  axi4buf_1_reset; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_aw_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_aw_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_aw_bits_id; // @[Buffer.scala 58:29]
  wire [11:0] axi4buf_1_auto_in_aw_bits_addr; // @[Buffer.scala 58:29]
  wire [7:0] axi4buf_1_auto_in_aw_bits_len; // @[Buffer.scala 58:29]
  wire [2:0] axi4buf_1_auto_in_aw_bits_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_in_aw_bits_burst; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_in_aw_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_in_aw_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_w_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_w_valid; // @[Buffer.scala 58:29]
  wire [31:0] axi4buf_1_auto_in_w_bits_data; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_in_w_bits_strb; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_w_bits_last; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_b_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_b_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_b_bits_id; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_in_b_bits_resp; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_in_b_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_in_b_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_ar_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_ar_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_ar_bits_id; // @[Buffer.scala 58:29]
  wire [11:0] axi4buf_1_auto_in_ar_bits_addr; // @[Buffer.scala 58:29]
  wire [7:0] axi4buf_1_auto_in_ar_bits_len; // @[Buffer.scala 58:29]
  wire [2:0] axi4buf_1_auto_in_ar_bits_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_in_ar_bits_burst; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_in_ar_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_in_ar_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_r_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_r_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_r_bits_id; // @[Buffer.scala 58:29]
  wire [31:0] axi4buf_1_auto_in_r_bits_data; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_in_r_bits_resp; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_in_r_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_in_r_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_in_r_bits_last; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_aw_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_aw_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_aw_bits_id; // @[Buffer.scala 58:29]
  wire [11:0] axi4buf_1_auto_out_aw_bits_addr; // @[Buffer.scala 58:29]
  wire [7:0] axi4buf_1_auto_out_aw_bits_len; // @[Buffer.scala 58:29]
  wire [2:0] axi4buf_1_auto_out_aw_bits_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_out_aw_bits_burst; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_out_aw_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_out_aw_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_w_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_w_valid; // @[Buffer.scala 58:29]
  wire [31:0] axi4buf_1_auto_out_w_bits_data; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_out_w_bits_strb; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_w_bits_last; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_b_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_b_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_b_bits_id; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_out_b_bits_resp; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_out_b_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_out_b_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_ar_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_ar_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_ar_bits_id; // @[Buffer.scala 58:29]
  wire [11:0] axi4buf_1_auto_out_ar_bits_addr; // @[Buffer.scala 58:29]
  wire [7:0] axi4buf_1_auto_out_ar_bits_len; // @[Buffer.scala 58:29]
  wire [2:0] axi4buf_1_auto_out_ar_bits_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_out_ar_bits_burst; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_out_ar_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_out_ar_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_r_ready; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_r_valid; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_r_bits_id; // @[Buffer.scala 58:29]
  wire [31:0] axi4buf_1_auto_out_r_bits_data; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_out_r_bits_resp; // @[Buffer.scala 58:29]
  wire [3:0] axi4buf_1_auto_out_r_bits_echo_tl_state_size; // @[Buffer.scala 58:29]
  wire [1:0] axi4buf_1_auto_out_r_bits_echo_tl_state_source; // @[Buffer.scala 58:29]
  wire  axi4buf_1_auto_out_r_bits_last; // @[Buffer.scala 58:29]
  wire  axi4delay_clock; // @[Delayer.scala 78:31]
  wire  axi4delay_reset; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_aw_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_aw_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_aw_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_auto_in_aw_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_auto_in_aw_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_auto_in_aw_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_in_aw_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_in_aw_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_in_aw_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_w_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_w_valid; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_auto_in_w_bits_data; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_in_w_bits_strb; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_w_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_b_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_b_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_b_bits_id; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_in_b_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_in_b_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_in_b_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_ar_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_ar_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_ar_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_auto_in_ar_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_auto_in_ar_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_auto_in_ar_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_in_ar_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_in_ar_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_in_ar_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_r_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_r_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_r_bits_id; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_auto_in_r_bits_data; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_in_r_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_in_r_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_in_r_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_in_r_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_aw_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_aw_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_aw_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_auto_out_aw_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_auto_out_aw_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_auto_out_aw_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_out_aw_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_out_aw_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_out_aw_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_w_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_w_valid; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_auto_out_w_bits_data; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_out_w_bits_strb; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_w_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_b_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_b_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_b_bits_id; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_out_b_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_out_b_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_out_b_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_ar_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_ar_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_ar_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_auto_out_ar_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_auto_out_ar_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_auto_out_ar_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_out_ar_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_out_ar_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_out_ar_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_r_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_r_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_r_bits_id; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_auto_out_r_bits_data; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_out_r_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_auto_out_r_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_auto_out_r_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_auto_out_r_bits_last; // @[Delayer.scala 78:31]
  wire  masters_clock; // @[Xbar.scala 306:48]
  wire  masters_reset; // @[Xbar.scala 306:48]
  wire  masters_auto_out_a_ready; // @[Xbar.scala 306:48]
  wire  masters_auto_out_a_valid; // @[Xbar.scala 306:48]
  wire [2:0] masters_auto_out_a_bits_opcode; // @[Xbar.scala 306:48]
  wire [3:0] masters_auto_out_a_bits_size; // @[Xbar.scala 306:48]
  wire [1:0] masters_auto_out_a_bits_source; // @[Xbar.scala 306:48]
  wire [10:0] masters_auto_out_a_bits_address; // @[Xbar.scala 306:48]
  wire [3:0] masters_auto_out_a_bits_mask; // @[Xbar.scala 306:48]
  wire [31:0] masters_auto_out_a_bits_data; // @[Xbar.scala 306:48]
  wire  masters_auto_out_d_valid; // @[Xbar.scala 306:48]
  wire [2:0] masters_auto_out_d_bits_opcode; // @[Xbar.scala 306:48]
  wire [3:0] masters_auto_out_d_bits_size; // @[Xbar.scala 306:48]
  wire [1:0] masters_auto_out_d_bits_source; // @[Xbar.scala 306:48]
  wire  masters_io_finished; // @[Xbar.scala 306:48]
  wire  masters_1_clock; // @[Xbar.scala 306:48]
  wire  masters_1_reset; // @[Xbar.scala 306:48]
  wire  masters_1_auto_out_a_ready; // @[Xbar.scala 306:48]
  wire  masters_1_auto_out_a_valid; // @[Xbar.scala 306:48]
  wire [2:0] masters_1_auto_out_a_bits_opcode; // @[Xbar.scala 306:48]
  wire [3:0] masters_1_auto_out_a_bits_size; // @[Xbar.scala 306:48]
  wire [1:0] masters_1_auto_out_a_bits_source; // @[Xbar.scala 306:48]
  wire [11:0] masters_1_auto_out_a_bits_address; // @[Xbar.scala 306:48]
  wire [3:0] masters_1_auto_out_a_bits_mask; // @[Xbar.scala 306:48]
  wire [31:0] masters_1_auto_out_a_bits_data; // @[Xbar.scala 306:48]
  wire  masters_1_auto_out_d_valid; // @[Xbar.scala 306:48]
  wire [2:0] masters_1_auto_out_d_bits_opcode; // @[Xbar.scala 306:48]
  wire [3:0] masters_1_auto_out_d_bits_size; // @[Xbar.scala 306:48]
  wire [1:0] masters_1_auto_out_d_bits_source; // @[Xbar.scala 306:48]
  wire  masters_1_io_finished; // @[Xbar.scala 306:48]
  wire  axi4delay_1_clock; // @[Delayer.scala 78:31]
  wire  axi4delay_1_reset; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_aw_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_aw_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_aw_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_1_auto_in_aw_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_1_auto_in_aw_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_1_auto_in_aw_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_in_aw_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_in_aw_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_in_aw_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_w_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_w_valid; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_1_auto_in_w_bits_data; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_in_w_bits_strb; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_w_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_b_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_b_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_b_bits_id; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_in_b_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_in_b_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_in_b_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_ar_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_ar_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_ar_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_1_auto_in_ar_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_1_auto_in_ar_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_1_auto_in_ar_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_in_ar_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_in_ar_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_in_ar_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_r_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_r_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_r_bits_id; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_1_auto_in_r_bits_data; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_in_r_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_in_r_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_in_r_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_in_r_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_aw_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_aw_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_aw_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_1_auto_out_aw_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_1_auto_out_aw_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_1_auto_out_aw_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_out_aw_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_out_aw_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_out_aw_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_w_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_w_valid; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_1_auto_out_w_bits_data; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_out_w_bits_strb; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_w_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_b_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_b_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_b_bits_id; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_out_b_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_out_b_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_out_b_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_ar_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_ar_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_ar_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_1_auto_out_ar_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_1_auto_out_ar_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_1_auto_out_ar_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_out_ar_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_out_ar_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_out_ar_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_r_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_r_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_r_bits_id; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_1_auto_out_r_bits_data; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_out_r_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_1_auto_out_r_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_1_auto_out_r_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_1_auto_out_r_bits_last; // @[Delayer.scala 78:31]
  wire  axi4deint_clock; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_reset; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_aw_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_aw_valid; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_aw_bits_id; // @[Deinterleaver.scala 140:31]
  wire [11:0] axi4deint_auto_in_aw_bits_addr; // @[Deinterleaver.scala 140:31]
  wire [7:0] axi4deint_auto_in_aw_bits_len; // @[Deinterleaver.scala 140:31]
  wire [2:0] axi4deint_auto_in_aw_bits_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_in_aw_bits_burst; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_in_aw_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_in_aw_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_w_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_w_valid; // @[Deinterleaver.scala 140:31]
  wire [31:0] axi4deint_auto_in_w_bits_data; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_in_w_bits_strb; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_w_bits_last; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_b_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_b_valid; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_in_b_bits_resp; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_in_b_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_in_b_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_ar_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_ar_valid; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_ar_bits_id; // @[Deinterleaver.scala 140:31]
  wire [11:0] axi4deint_auto_in_ar_bits_addr; // @[Deinterleaver.scala 140:31]
  wire [7:0] axi4deint_auto_in_ar_bits_len; // @[Deinterleaver.scala 140:31]
  wire [2:0] axi4deint_auto_in_ar_bits_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_in_ar_bits_burst; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_in_ar_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_in_ar_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_r_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_r_valid; // @[Deinterleaver.scala 140:31]
  wire [31:0] axi4deint_auto_in_r_bits_data; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_in_r_bits_resp; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_in_r_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_in_r_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_in_r_bits_last; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_aw_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_aw_valid; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_aw_bits_id; // @[Deinterleaver.scala 140:31]
  wire [11:0] axi4deint_auto_out_aw_bits_addr; // @[Deinterleaver.scala 140:31]
  wire [7:0] axi4deint_auto_out_aw_bits_len; // @[Deinterleaver.scala 140:31]
  wire [2:0] axi4deint_auto_out_aw_bits_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_out_aw_bits_burst; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_out_aw_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_out_aw_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_w_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_w_valid; // @[Deinterleaver.scala 140:31]
  wire [31:0] axi4deint_auto_out_w_bits_data; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_out_w_bits_strb; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_w_bits_last; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_b_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_b_valid; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_out_b_bits_resp; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_out_b_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_out_b_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_ar_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_ar_valid; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_ar_bits_id; // @[Deinterleaver.scala 140:31]
  wire [11:0] axi4deint_auto_out_ar_bits_addr; // @[Deinterleaver.scala 140:31]
  wire [7:0] axi4deint_auto_out_ar_bits_len; // @[Deinterleaver.scala 140:31]
  wire [2:0] axi4deint_auto_out_ar_bits_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_out_ar_bits_burst; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_out_ar_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_out_ar_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_r_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_r_valid; // @[Deinterleaver.scala 140:31]
  wire [31:0] axi4deint_auto_out_r_bits_data; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_out_r_bits_resp; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_auto_out_r_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_auto_out_r_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_auto_out_r_bits_last; // @[Deinterleaver.scala 140:31]
  wire  tl2axi4_clock; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_reset; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_in_a_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_in_a_valid; // @[ToAXI4.scala 283:29]
  wire [2:0] tl2axi4_auto_in_a_bits_opcode; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_auto_in_a_bits_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_in_a_bits_source; // @[ToAXI4.scala 283:29]
  wire [11:0] tl2axi4_auto_in_a_bits_address; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_auto_in_a_bits_mask; // @[ToAXI4.scala 283:29]
  wire [31:0] tl2axi4_auto_in_a_bits_data; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_in_d_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_in_d_valid; // @[ToAXI4.scala 283:29]
  wire [2:0] tl2axi4_auto_in_d_bits_opcode; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_auto_in_d_bits_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_in_d_bits_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_in_d_bits_denied; // @[ToAXI4.scala 283:29]
  wire [31:0] tl2axi4_auto_in_d_bits_data; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_in_d_bits_corrupt; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_aw_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala 283:29]
  wire [11:0] tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala 283:29]
  wire [7:0] tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala 283:29]
  wire [2:0] tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_auto_out_aw_bits_echo_tl_state_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_out_aw_bits_echo_tl_state_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_w_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_w_valid; // @[ToAXI4.scala 283:29]
  wire [31:0] tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_b_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_b_valid; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_out_b_bits_resp; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_auto_out_b_bits_echo_tl_state_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_ar_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala 283:29]
  wire [11:0] tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala 283:29]
  wire [7:0] tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala 283:29]
  wire [2:0] tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_auto_out_ar_bits_echo_tl_state_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_out_ar_bits_echo_tl_state_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_r_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_r_valid; // @[ToAXI4.scala 283:29]
  wire [31:0] tl2axi4_auto_out_r_bits_data; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_out_r_bits_resp; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_auto_out_r_bits_echo_tl_state_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_auto_out_r_bits_echo_tl_state_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_auto_out_r_bits_last; // @[ToAXI4.scala 283:29]
  wire  filter_auto_in_a_ready; // @[Filter.scala 164:28]
  wire  filter_auto_in_a_valid; // @[Filter.scala 164:28]
  wire [2:0] filter_auto_in_a_bits_opcode; // @[Filter.scala 164:28]
  wire [3:0] filter_auto_in_a_bits_size; // @[Filter.scala 164:28]
  wire [1:0] filter_auto_in_a_bits_source; // @[Filter.scala 164:28]
  wire [10:0] filter_auto_in_a_bits_address; // @[Filter.scala 164:28]
  wire [3:0] filter_auto_in_a_bits_mask; // @[Filter.scala 164:28]
  wire [31:0] filter_auto_in_a_bits_data; // @[Filter.scala 164:28]
  wire  filter_auto_in_d_ready; // @[Filter.scala 164:28]
  wire  filter_auto_in_d_valid; // @[Filter.scala 164:28]
  wire [2:0] filter_auto_in_d_bits_opcode; // @[Filter.scala 164:28]
  wire [3:0] filter_auto_in_d_bits_size; // @[Filter.scala 164:28]
  wire [1:0] filter_auto_in_d_bits_source; // @[Filter.scala 164:28]
  wire  filter_auto_in_d_bits_denied; // @[Filter.scala 164:28]
  wire [31:0] filter_auto_in_d_bits_data; // @[Filter.scala 164:28]
  wire  filter_auto_in_d_bits_corrupt; // @[Filter.scala 164:28]
  wire  filter_auto_out_a_ready; // @[Filter.scala 164:28]
  wire  filter_auto_out_a_valid; // @[Filter.scala 164:28]
  wire [2:0] filter_auto_out_a_bits_opcode; // @[Filter.scala 164:28]
  wire [3:0] filter_auto_out_a_bits_size; // @[Filter.scala 164:28]
  wire [1:0] filter_auto_out_a_bits_source; // @[Filter.scala 164:28]
  wire [11:0] filter_auto_out_a_bits_address; // @[Filter.scala 164:28]
  wire [3:0] filter_auto_out_a_bits_mask; // @[Filter.scala 164:28]
  wire [31:0] filter_auto_out_a_bits_data; // @[Filter.scala 164:28]
  wire  filter_auto_out_d_ready; // @[Filter.scala 164:28]
  wire  filter_auto_out_d_valid; // @[Filter.scala 164:28]
  wire [2:0] filter_auto_out_d_bits_opcode; // @[Filter.scala 164:28]
  wire [3:0] filter_auto_out_d_bits_size; // @[Filter.scala 164:28]
  wire [1:0] filter_auto_out_d_bits_source; // @[Filter.scala 164:28]
  wire  filter_auto_out_d_bits_denied; // @[Filter.scala 164:28]
  wire [31:0] filter_auto_out_d_bits_data; // @[Filter.scala 164:28]
  wire  filter_auto_out_d_bits_corrupt; // @[Filter.scala 164:28]
  wire  model_clock; // @[RAMModel.scala 340:27]
  wire  model_reset; // @[RAMModel.scala 340:27]
  wire  model_auto_in_a_ready; // @[RAMModel.scala 340:27]
  wire  model_auto_in_a_valid; // @[RAMModel.scala 340:27]
  wire [2:0] model_auto_in_a_bits_opcode; // @[RAMModel.scala 340:27]
  wire [3:0] model_auto_in_a_bits_size; // @[RAMModel.scala 340:27]
  wire [1:0] model_auto_in_a_bits_source; // @[RAMModel.scala 340:27]
  wire [10:0] model_auto_in_a_bits_address; // @[RAMModel.scala 340:27]
  wire [3:0] model_auto_in_a_bits_mask; // @[RAMModel.scala 340:27]
  wire [31:0] model_auto_in_a_bits_data; // @[RAMModel.scala 340:27]
  wire  model_auto_in_d_valid; // @[RAMModel.scala 340:27]
  wire [2:0] model_auto_in_d_bits_opcode; // @[RAMModel.scala 340:27]
  wire [3:0] model_auto_in_d_bits_size; // @[RAMModel.scala 340:27]
  wire [1:0] model_auto_in_d_bits_source; // @[RAMModel.scala 340:27]
  wire  model_auto_out_a_ready; // @[RAMModel.scala 340:27]
  wire  model_auto_out_a_valid; // @[RAMModel.scala 340:27]
  wire [2:0] model_auto_out_a_bits_opcode; // @[RAMModel.scala 340:27]
  wire [3:0] model_auto_out_a_bits_size; // @[RAMModel.scala 340:27]
  wire [1:0] model_auto_out_a_bits_source; // @[RAMModel.scala 340:27]
  wire [10:0] model_auto_out_a_bits_address; // @[RAMModel.scala 340:27]
  wire [3:0] model_auto_out_a_bits_mask; // @[RAMModel.scala 340:27]
  wire [31:0] model_auto_out_a_bits_data; // @[RAMModel.scala 340:27]
  wire  model_auto_out_d_ready; // @[RAMModel.scala 340:27]
  wire  model_auto_out_d_valid; // @[RAMModel.scala 340:27]
  wire [2:0] model_auto_out_d_bits_opcode; // @[RAMModel.scala 340:27]
  wire [3:0] model_auto_out_d_bits_size; // @[RAMModel.scala 340:27]
  wire [1:0] model_auto_out_d_bits_source; // @[RAMModel.scala 340:27]
  wire  model_auto_out_d_bits_denied; // @[RAMModel.scala 340:27]
  wire [31:0] model_auto_out_d_bits_data; // @[RAMModel.scala 340:27]
  wire  model_auto_out_d_bits_corrupt; // @[RAMModel.scala 340:27]
  wire  axi4delay_2_clock; // @[Delayer.scala 78:31]
  wire  axi4delay_2_reset; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_aw_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_aw_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_aw_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_2_auto_in_aw_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_2_auto_in_aw_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_2_auto_in_aw_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_in_aw_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_in_aw_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_in_aw_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_w_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_w_valid; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_2_auto_in_w_bits_data; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_in_w_bits_strb; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_w_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_b_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_b_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_b_bits_id; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_in_b_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_in_b_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_in_b_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_ar_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_ar_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_ar_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_2_auto_in_ar_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_2_auto_in_ar_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_2_auto_in_ar_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_in_ar_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_in_ar_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_in_ar_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_r_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_r_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_r_bits_id; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_2_auto_in_r_bits_data; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_in_r_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_in_r_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_in_r_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_in_r_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_aw_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_aw_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_aw_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_2_auto_out_aw_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_2_auto_out_aw_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_2_auto_out_aw_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_out_aw_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_out_aw_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_out_aw_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_w_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_w_valid; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_2_auto_out_w_bits_data; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_out_w_bits_strb; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_w_bits_last; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_b_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_b_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_b_bits_id; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_out_b_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_out_b_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_out_b_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_ar_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_ar_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_ar_bits_id; // @[Delayer.scala 78:31]
  wire [11:0] axi4delay_2_auto_out_ar_bits_addr; // @[Delayer.scala 78:31]
  wire [7:0] axi4delay_2_auto_out_ar_bits_len; // @[Delayer.scala 78:31]
  wire [2:0] axi4delay_2_auto_out_ar_bits_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_out_ar_bits_burst; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_out_ar_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_out_ar_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_r_ready; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_r_valid; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_r_bits_id; // @[Delayer.scala 78:31]
  wire [31:0] axi4delay_2_auto_out_r_bits_data; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_out_r_bits_resp; // @[Delayer.scala 78:31]
  wire [3:0] axi4delay_2_auto_out_r_bits_echo_tl_state_size; // @[Delayer.scala 78:31]
  wire [1:0] axi4delay_2_auto_out_r_bits_echo_tl_state_source; // @[Delayer.scala 78:31]
  wire  axi4delay_2_auto_out_r_bits_last; // @[Delayer.scala 78:31]
  wire  axi4deint_1_clock; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_reset; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_aw_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_aw_valid; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_aw_bits_id; // @[Deinterleaver.scala 140:31]
  wire [11:0] axi4deint_1_auto_in_aw_bits_addr; // @[Deinterleaver.scala 140:31]
  wire [7:0] axi4deint_1_auto_in_aw_bits_len; // @[Deinterleaver.scala 140:31]
  wire [2:0] axi4deint_1_auto_in_aw_bits_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_in_aw_bits_burst; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_in_aw_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_in_aw_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_w_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_w_valid; // @[Deinterleaver.scala 140:31]
  wire [31:0] axi4deint_1_auto_in_w_bits_data; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_in_w_bits_strb; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_w_bits_last; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_b_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_b_valid; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_in_b_bits_resp; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_in_b_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_in_b_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_ar_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_ar_valid; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_ar_bits_id; // @[Deinterleaver.scala 140:31]
  wire [11:0] axi4deint_1_auto_in_ar_bits_addr; // @[Deinterleaver.scala 140:31]
  wire [7:0] axi4deint_1_auto_in_ar_bits_len; // @[Deinterleaver.scala 140:31]
  wire [2:0] axi4deint_1_auto_in_ar_bits_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_in_ar_bits_burst; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_in_ar_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_in_ar_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_r_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_r_valid; // @[Deinterleaver.scala 140:31]
  wire [31:0] axi4deint_1_auto_in_r_bits_data; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_in_r_bits_resp; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_in_r_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_in_r_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_in_r_bits_last; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_aw_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_aw_valid; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_aw_bits_id; // @[Deinterleaver.scala 140:31]
  wire [11:0] axi4deint_1_auto_out_aw_bits_addr; // @[Deinterleaver.scala 140:31]
  wire [7:0] axi4deint_1_auto_out_aw_bits_len; // @[Deinterleaver.scala 140:31]
  wire [2:0] axi4deint_1_auto_out_aw_bits_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_out_aw_bits_burst; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_out_aw_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_out_aw_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_w_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_w_valid; // @[Deinterleaver.scala 140:31]
  wire [31:0] axi4deint_1_auto_out_w_bits_data; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_out_w_bits_strb; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_w_bits_last; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_b_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_b_valid; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_out_b_bits_resp; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_out_b_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_out_b_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_ar_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_ar_valid; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_ar_bits_id; // @[Deinterleaver.scala 140:31]
  wire [11:0] axi4deint_1_auto_out_ar_bits_addr; // @[Deinterleaver.scala 140:31]
  wire [7:0] axi4deint_1_auto_out_ar_bits_len; // @[Deinterleaver.scala 140:31]
  wire [2:0] axi4deint_1_auto_out_ar_bits_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_out_ar_bits_burst; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_out_ar_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_out_ar_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_r_ready; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_r_valid; // @[Deinterleaver.scala 140:31]
  wire [31:0] axi4deint_1_auto_out_r_bits_data; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_out_r_bits_resp; // @[Deinterleaver.scala 140:31]
  wire [3:0] axi4deint_1_auto_out_r_bits_echo_tl_state_size; // @[Deinterleaver.scala 140:31]
  wire [1:0] axi4deint_1_auto_out_r_bits_echo_tl_state_source; // @[Deinterleaver.scala 140:31]
  wire  axi4deint_1_auto_out_r_bits_last; // @[Deinterleaver.scala 140:31]
  wire  tl2axi4_1_clock; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_reset; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_in_a_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_in_a_valid; // @[ToAXI4.scala 283:29]
  wire [2:0] tl2axi4_1_auto_in_a_bits_opcode; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_1_auto_in_a_bits_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_in_a_bits_source; // @[ToAXI4.scala 283:29]
  wire [11:0] tl2axi4_1_auto_in_a_bits_address; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_1_auto_in_a_bits_mask; // @[ToAXI4.scala 283:29]
  wire [31:0] tl2axi4_1_auto_in_a_bits_data; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_in_d_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_in_d_valid; // @[ToAXI4.scala 283:29]
  wire [2:0] tl2axi4_1_auto_in_d_bits_opcode; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_1_auto_in_d_bits_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_in_d_bits_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_in_d_bits_denied; // @[ToAXI4.scala 283:29]
  wire [31:0] tl2axi4_1_auto_in_d_bits_data; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_in_d_bits_corrupt; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_aw_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_aw_valid; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_aw_bits_id; // @[ToAXI4.scala 283:29]
  wire [11:0] tl2axi4_1_auto_out_aw_bits_addr; // @[ToAXI4.scala 283:29]
  wire [7:0] tl2axi4_1_auto_out_aw_bits_len; // @[ToAXI4.scala 283:29]
  wire [2:0] tl2axi4_1_auto_out_aw_bits_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_out_aw_bits_burst; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_1_auto_out_aw_bits_echo_tl_state_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_out_aw_bits_echo_tl_state_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_w_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_w_valid; // @[ToAXI4.scala 283:29]
  wire [31:0] tl2axi4_1_auto_out_w_bits_data; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_1_auto_out_w_bits_strb; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_w_bits_last; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_b_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_b_valid; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_out_b_bits_resp; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_1_auto_out_b_bits_echo_tl_state_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_ar_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_ar_valid; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_ar_bits_id; // @[ToAXI4.scala 283:29]
  wire [11:0] tl2axi4_1_auto_out_ar_bits_addr; // @[ToAXI4.scala 283:29]
  wire [7:0] tl2axi4_1_auto_out_ar_bits_len; // @[ToAXI4.scala 283:29]
  wire [2:0] tl2axi4_1_auto_out_ar_bits_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_out_ar_bits_burst; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_1_auto_out_ar_bits_echo_tl_state_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_out_ar_bits_echo_tl_state_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_r_ready; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_r_valid; // @[ToAXI4.scala 283:29]
  wire [31:0] tl2axi4_1_auto_out_r_bits_data; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_out_r_bits_resp; // @[ToAXI4.scala 283:29]
  wire [3:0] tl2axi4_1_auto_out_r_bits_echo_tl_state_size; // @[ToAXI4.scala 283:29]
  wire [1:0] tl2axi4_1_auto_out_r_bits_echo_tl_state_source; // @[ToAXI4.scala 283:29]
  wire  tl2axi4_1_auto_out_r_bits_last; // @[ToAXI4.scala 283:29]
  wire  filter_1_auto_in_a_ready; // @[Filter.scala 164:28]
  wire  filter_1_auto_in_a_valid; // @[Filter.scala 164:28]
  wire [2:0] filter_1_auto_in_a_bits_opcode; // @[Filter.scala 164:28]
  wire [3:0] filter_1_auto_in_a_bits_size; // @[Filter.scala 164:28]
  wire [1:0] filter_1_auto_in_a_bits_source; // @[Filter.scala 164:28]
  wire [11:0] filter_1_auto_in_a_bits_address; // @[Filter.scala 164:28]
  wire [3:0] filter_1_auto_in_a_bits_mask; // @[Filter.scala 164:28]
  wire [31:0] filter_1_auto_in_a_bits_data; // @[Filter.scala 164:28]
  wire  filter_1_auto_in_d_ready; // @[Filter.scala 164:28]
  wire  filter_1_auto_in_d_valid; // @[Filter.scala 164:28]
  wire [2:0] filter_1_auto_in_d_bits_opcode; // @[Filter.scala 164:28]
  wire [3:0] filter_1_auto_in_d_bits_size; // @[Filter.scala 164:28]
  wire [1:0] filter_1_auto_in_d_bits_source; // @[Filter.scala 164:28]
  wire  filter_1_auto_in_d_bits_denied; // @[Filter.scala 164:28]
  wire [31:0] filter_1_auto_in_d_bits_data; // @[Filter.scala 164:28]
  wire  filter_1_auto_in_d_bits_corrupt; // @[Filter.scala 164:28]
  wire  filter_1_auto_out_a_ready; // @[Filter.scala 164:28]
  wire  filter_1_auto_out_a_valid; // @[Filter.scala 164:28]
  wire [2:0] filter_1_auto_out_a_bits_opcode; // @[Filter.scala 164:28]
  wire [3:0] filter_1_auto_out_a_bits_size; // @[Filter.scala 164:28]
  wire [1:0] filter_1_auto_out_a_bits_source; // @[Filter.scala 164:28]
  wire [11:0] filter_1_auto_out_a_bits_address; // @[Filter.scala 164:28]
  wire [3:0] filter_1_auto_out_a_bits_mask; // @[Filter.scala 164:28]
  wire [31:0] filter_1_auto_out_a_bits_data; // @[Filter.scala 164:28]
  wire  filter_1_auto_out_d_ready; // @[Filter.scala 164:28]
  wire  filter_1_auto_out_d_valid; // @[Filter.scala 164:28]
  wire [2:0] filter_1_auto_out_d_bits_opcode; // @[Filter.scala 164:28]
  wire [3:0] filter_1_auto_out_d_bits_size; // @[Filter.scala 164:28]
  wire [1:0] filter_1_auto_out_d_bits_source; // @[Filter.scala 164:28]
  wire  filter_1_auto_out_d_bits_denied; // @[Filter.scala 164:28]
  wire [31:0] filter_1_auto_out_d_bits_data; // @[Filter.scala 164:28]
  wire  filter_1_auto_out_d_bits_corrupt; // @[Filter.scala 164:28]
  wire  model_1_clock; // @[RAMModel.scala 340:27]
  wire  model_1_reset; // @[RAMModel.scala 340:27]
  wire  model_1_auto_in_a_ready; // @[RAMModel.scala 340:27]
  wire  model_1_auto_in_a_valid; // @[RAMModel.scala 340:27]
  wire [2:0] model_1_auto_in_a_bits_opcode; // @[RAMModel.scala 340:27]
  wire [3:0] model_1_auto_in_a_bits_size; // @[RAMModel.scala 340:27]
  wire [1:0] model_1_auto_in_a_bits_source; // @[RAMModel.scala 340:27]
  wire [11:0] model_1_auto_in_a_bits_address; // @[RAMModel.scala 340:27]
  wire [3:0] model_1_auto_in_a_bits_mask; // @[RAMModel.scala 340:27]
  wire [31:0] model_1_auto_in_a_bits_data; // @[RAMModel.scala 340:27]
  wire  model_1_auto_in_d_valid; // @[RAMModel.scala 340:27]
  wire [2:0] model_1_auto_in_d_bits_opcode; // @[RAMModel.scala 340:27]
  wire [3:0] model_1_auto_in_d_bits_size; // @[RAMModel.scala 340:27]
  wire [1:0] model_1_auto_in_d_bits_source; // @[RAMModel.scala 340:27]
  wire  model_1_auto_out_a_ready; // @[RAMModel.scala 340:27]
  wire  model_1_auto_out_a_valid; // @[RAMModel.scala 340:27]
  wire [2:0] model_1_auto_out_a_bits_opcode; // @[RAMModel.scala 340:27]
  wire [3:0] model_1_auto_out_a_bits_size; // @[RAMModel.scala 340:27]
  wire [1:0] model_1_auto_out_a_bits_source; // @[RAMModel.scala 340:27]
  wire [11:0] model_1_auto_out_a_bits_address; // @[RAMModel.scala 340:27]
  wire [3:0] model_1_auto_out_a_bits_mask; // @[RAMModel.scala 340:27]
  wire [31:0] model_1_auto_out_a_bits_data; // @[RAMModel.scala 340:27]
  wire  model_1_auto_out_d_ready; // @[RAMModel.scala 340:27]
  wire  model_1_auto_out_d_valid; // @[RAMModel.scala 340:27]
  wire [2:0] model_1_auto_out_d_bits_opcode; // @[RAMModel.scala 340:27]
  wire [3:0] model_1_auto_out_d_bits_size; // @[RAMModel.scala 340:27]
  wire [1:0] model_1_auto_out_d_bits_source; // @[RAMModel.scala 340:27]
  wire  model_1_auto_out_d_bits_denied; // @[RAMModel.scala 340:27]
  wire [31:0] model_1_auto_out_d_bits_data; // @[RAMModel.scala 340:27]
  wire  model_1_auto_out_d_bits_corrupt; // @[RAMModel.scala 340:27]
  AXI4Xbar axi4xbar ( // @[Xbar.scala 218:30]
    .clock(axi4xbar_clock),
    .reset(axi4xbar_reset),
    .auto_in_1_aw_ready(axi4xbar_auto_in_1_aw_ready),
    .auto_in_1_aw_valid(axi4xbar_auto_in_1_aw_valid),
    .auto_in_1_aw_bits_id(axi4xbar_auto_in_1_aw_bits_id),
    .auto_in_1_aw_bits_addr(axi4xbar_auto_in_1_aw_bits_addr),
    .auto_in_1_aw_bits_len(axi4xbar_auto_in_1_aw_bits_len),
    .auto_in_1_aw_bits_size(axi4xbar_auto_in_1_aw_bits_size),
    .auto_in_1_aw_bits_burst(axi4xbar_auto_in_1_aw_bits_burst),
    .auto_in_1_aw_bits_echo_tl_state_size(axi4xbar_auto_in_1_aw_bits_echo_tl_state_size),
    .auto_in_1_aw_bits_echo_tl_state_source(axi4xbar_auto_in_1_aw_bits_echo_tl_state_source),
    .auto_in_1_w_ready(axi4xbar_auto_in_1_w_ready),
    .auto_in_1_w_valid(axi4xbar_auto_in_1_w_valid),
    .auto_in_1_w_bits_data(axi4xbar_auto_in_1_w_bits_data),
    .auto_in_1_w_bits_strb(axi4xbar_auto_in_1_w_bits_strb),
    .auto_in_1_w_bits_last(axi4xbar_auto_in_1_w_bits_last),
    .auto_in_1_b_ready(axi4xbar_auto_in_1_b_ready),
    .auto_in_1_b_valid(axi4xbar_auto_in_1_b_valid),
    .auto_in_1_b_bits_resp(axi4xbar_auto_in_1_b_bits_resp),
    .auto_in_1_b_bits_echo_tl_state_size(axi4xbar_auto_in_1_b_bits_echo_tl_state_size),
    .auto_in_1_b_bits_echo_tl_state_source(axi4xbar_auto_in_1_b_bits_echo_tl_state_source),
    .auto_in_1_ar_ready(axi4xbar_auto_in_1_ar_ready),
    .auto_in_1_ar_valid(axi4xbar_auto_in_1_ar_valid),
    .auto_in_1_ar_bits_id(axi4xbar_auto_in_1_ar_bits_id),
    .auto_in_1_ar_bits_addr(axi4xbar_auto_in_1_ar_bits_addr),
    .auto_in_1_ar_bits_len(axi4xbar_auto_in_1_ar_bits_len),
    .auto_in_1_ar_bits_size(axi4xbar_auto_in_1_ar_bits_size),
    .auto_in_1_ar_bits_burst(axi4xbar_auto_in_1_ar_bits_burst),
    .auto_in_1_ar_bits_echo_tl_state_size(axi4xbar_auto_in_1_ar_bits_echo_tl_state_size),
    .auto_in_1_ar_bits_echo_tl_state_source(axi4xbar_auto_in_1_ar_bits_echo_tl_state_source),
    .auto_in_1_r_ready(axi4xbar_auto_in_1_r_ready),
    .auto_in_1_r_valid(axi4xbar_auto_in_1_r_valid),
    .auto_in_1_r_bits_data(axi4xbar_auto_in_1_r_bits_data),
    .auto_in_1_r_bits_resp(axi4xbar_auto_in_1_r_bits_resp),
    .auto_in_1_r_bits_echo_tl_state_size(axi4xbar_auto_in_1_r_bits_echo_tl_state_size),
    .auto_in_1_r_bits_echo_tl_state_source(axi4xbar_auto_in_1_r_bits_echo_tl_state_source),
    .auto_in_1_r_bits_last(axi4xbar_auto_in_1_r_bits_last),
    .auto_in_0_aw_ready(axi4xbar_auto_in_0_aw_ready),
    .auto_in_0_aw_valid(axi4xbar_auto_in_0_aw_valid),
    .auto_in_0_aw_bits_addr(axi4xbar_auto_in_0_aw_bits_addr),
    .auto_in_0_aw_bits_len(axi4xbar_auto_in_0_aw_bits_len),
    .auto_in_0_aw_bits_size(axi4xbar_auto_in_0_aw_bits_size),
    .auto_in_0_aw_bits_burst(axi4xbar_auto_in_0_aw_bits_burst),
    .auto_in_0_aw_bits_echo_tl_state_size(axi4xbar_auto_in_0_aw_bits_echo_tl_state_size),
    .auto_in_0_aw_bits_echo_tl_state_source(axi4xbar_auto_in_0_aw_bits_echo_tl_state_source),
    .auto_in_0_w_ready(axi4xbar_auto_in_0_w_ready),
    .auto_in_0_w_valid(axi4xbar_auto_in_0_w_valid),
    .auto_in_0_w_bits_data(axi4xbar_auto_in_0_w_bits_data),
    .auto_in_0_w_bits_strb(axi4xbar_auto_in_0_w_bits_strb),
    .auto_in_0_w_bits_last(axi4xbar_auto_in_0_w_bits_last),
    .auto_in_0_b_ready(axi4xbar_auto_in_0_b_ready),
    .auto_in_0_b_valid(axi4xbar_auto_in_0_b_valid),
    .auto_in_0_b_bits_resp(axi4xbar_auto_in_0_b_bits_resp),
    .auto_in_0_b_bits_echo_tl_state_size(axi4xbar_auto_in_0_b_bits_echo_tl_state_size),
    .auto_in_0_b_bits_echo_tl_state_source(axi4xbar_auto_in_0_b_bits_echo_tl_state_source),
    .auto_in_0_ar_ready(axi4xbar_auto_in_0_ar_ready),
    .auto_in_0_ar_valid(axi4xbar_auto_in_0_ar_valid),
    .auto_in_0_ar_bits_addr(axi4xbar_auto_in_0_ar_bits_addr),
    .auto_in_0_ar_bits_len(axi4xbar_auto_in_0_ar_bits_len),
    .auto_in_0_ar_bits_size(axi4xbar_auto_in_0_ar_bits_size),
    .auto_in_0_ar_bits_burst(axi4xbar_auto_in_0_ar_bits_burst),
    .auto_in_0_ar_bits_echo_tl_state_size(axi4xbar_auto_in_0_ar_bits_echo_tl_state_size),
    .auto_in_0_ar_bits_echo_tl_state_source(axi4xbar_auto_in_0_ar_bits_echo_tl_state_source),
    .auto_in_0_r_ready(axi4xbar_auto_in_0_r_ready),
    .auto_in_0_r_valid(axi4xbar_auto_in_0_r_valid),
    .auto_in_0_r_bits_data(axi4xbar_auto_in_0_r_bits_data),
    .auto_in_0_r_bits_resp(axi4xbar_auto_in_0_r_bits_resp),
    .auto_in_0_r_bits_echo_tl_state_size(axi4xbar_auto_in_0_r_bits_echo_tl_state_size),
    .auto_in_0_r_bits_echo_tl_state_source(axi4xbar_auto_in_0_r_bits_echo_tl_state_source),
    .auto_in_0_r_bits_last(axi4xbar_auto_in_0_r_bits_last),
    .auto_out_aw_ready(axi4xbar_auto_out_aw_ready),
    .auto_out_aw_valid(axi4xbar_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4xbar_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4xbar_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(axi4xbar_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(axi4xbar_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(axi4xbar_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(axi4xbar_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4xbar_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(axi4xbar_auto_out_w_ready),
    .auto_out_w_valid(axi4xbar_auto_out_w_valid),
    .auto_out_w_bits_data(axi4xbar_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4xbar_auto_out_w_bits_strb),
    .auto_out_w_bits_last(axi4xbar_auto_out_w_bits_last),
    .auto_out_b_ready(axi4xbar_auto_out_b_ready),
    .auto_out_b_valid(axi4xbar_auto_out_b_valid),
    .auto_out_b_bits_id(axi4xbar_auto_out_b_bits_id),
    .auto_out_b_bits_resp(axi4xbar_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4xbar_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4xbar_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(axi4xbar_auto_out_ar_ready),
    .auto_out_ar_valid(axi4xbar_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4xbar_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4xbar_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(axi4xbar_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(axi4xbar_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(axi4xbar_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(axi4xbar_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4xbar_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(axi4xbar_auto_out_r_ready),
    .auto_out_r_valid(axi4xbar_auto_out_r_valid),
    .auto_out_r_bits_id(axi4xbar_auto_out_r_bits_id),
    .auto_out_r_bits_data(axi4xbar_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4xbar_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4xbar_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4xbar_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(axi4xbar_auto_out_r_bits_last)
  );
  AXI4RAM slaves ( // @[Xbar.scala 298:55]
    .clock(slaves_clock),
    .reset(slaves_reset),
    .auto_in_aw_ready(slaves_auto_in_aw_ready),
    .auto_in_aw_valid(slaves_auto_in_aw_valid),
    .auto_in_aw_bits_id(slaves_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(slaves_auto_in_aw_bits_addr),
    .auto_in_aw_bits_echo_tl_state_size(slaves_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(slaves_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_aw_bits_echo_real_last(slaves_auto_in_aw_bits_echo_real_last),
    .auto_in_w_ready(slaves_auto_in_w_ready),
    .auto_in_w_valid(slaves_auto_in_w_valid),
    .auto_in_w_bits_data(slaves_auto_in_w_bits_data),
    .auto_in_w_bits_strb(slaves_auto_in_w_bits_strb),
    .auto_in_b_ready(slaves_auto_in_b_ready),
    .auto_in_b_valid(slaves_auto_in_b_valid),
    .auto_in_b_bits_id(slaves_auto_in_b_bits_id),
    .auto_in_b_bits_resp(slaves_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(slaves_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(slaves_auto_in_b_bits_echo_tl_state_source),
    .auto_in_b_bits_echo_real_last(slaves_auto_in_b_bits_echo_real_last),
    .auto_in_ar_ready(slaves_auto_in_ar_ready),
    .auto_in_ar_valid(slaves_auto_in_ar_valid),
    .auto_in_ar_bits_id(slaves_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(slaves_auto_in_ar_bits_addr),
    .auto_in_ar_bits_echo_tl_state_size(slaves_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(slaves_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_ar_bits_echo_real_last(slaves_auto_in_ar_bits_echo_real_last),
    .auto_in_r_ready(slaves_auto_in_r_ready),
    .auto_in_r_valid(slaves_auto_in_r_valid),
    .auto_in_r_bits_id(slaves_auto_in_r_bits_id),
    .auto_in_r_bits_data(slaves_auto_in_r_bits_data),
    .auto_in_r_bits_resp(slaves_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(slaves_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(slaves_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_echo_real_last(slaves_auto_in_r_bits_echo_real_last)
  );
  AXI4Fragmenter axi4frag ( // @[Fragmenter.scala 205:30]
    .clock(axi4frag_clock),
    .reset(axi4frag_reset),
    .auto_in_aw_ready(axi4frag_auto_in_aw_ready),
    .auto_in_aw_valid(axi4frag_auto_in_aw_valid),
    .auto_in_aw_bits_id(axi4frag_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(axi4frag_auto_in_aw_bits_addr),
    .auto_in_aw_bits_len(axi4frag_auto_in_aw_bits_len),
    .auto_in_aw_bits_size(axi4frag_auto_in_aw_bits_size),
    .auto_in_aw_bits_burst(axi4frag_auto_in_aw_bits_burst),
    .auto_in_aw_bits_echo_tl_state_size(axi4frag_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(axi4frag_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_w_ready(axi4frag_auto_in_w_ready),
    .auto_in_w_valid(axi4frag_auto_in_w_valid),
    .auto_in_w_bits_data(axi4frag_auto_in_w_bits_data),
    .auto_in_w_bits_strb(axi4frag_auto_in_w_bits_strb),
    .auto_in_w_bits_last(axi4frag_auto_in_w_bits_last),
    .auto_in_b_ready(axi4frag_auto_in_b_ready),
    .auto_in_b_valid(axi4frag_auto_in_b_valid),
    .auto_in_b_bits_id(axi4frag_auto_in_b_bits_id),
    .auto_in_b_bits_resp(axi4frag_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(axi4frag_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(axi4frag_auto_in_b_bits_echo_tl_state_source),
    .auto_in_ar_ready(axi4frag_auto_in_ar_ready),
    .auto_in_ar_valid(axi4frag_auto_in_ar_valid),
    .auto_in_ar_bits_id(axi4frag_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(axi4frag_auto_in_ar_bits_addr),
    .auto_in_ar_bits_len(axi4frag_auto_in_ar_bits_len),
    .auto_in_ar_bits_size(axi4frag_auto_in_ar_bits_size),
    .auto_in_ar_bits_burst(axi4frag_auto_in_ar_bits_burst),
    .auto_in_ar_bits_echo_tl_state_size(axi4frag_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(axi4frag_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_r_ready(axi4frag_auto_in_r_ready),
    .auto_in_r_valid(axi4frag_auto_in_r_valid),
    .auto_in_r_bits_id(axi4frag_auto_in_r_bits_id),
    .auto_in_r_bits_data(axi4frag_auto_in_r_bits_data),
    .auto_in_r_bits_resp(axi4frag_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(axi4frag_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(axi4frag_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_last(axi4frag_auto_in_r_bits_last),
    .auto_out_aw_ready(axi4frag_auto_out_aw_ready),
    .auto_out_aw_valid(axi4frag_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4frag_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4frag_auto_out_aw_bits_addr),
    .auto_out_aw_bits_echo_tl_state_size(axi4frag_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4frag_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_aw_bits_echo_real_last(axi4frag_auto_out_aw_bits_echo_real_last),
    .auto_out_w_ready(axi4frag_auto_out_w_ready),
    .auto_out_w_valid(axi4frag_auto_out_w_valid),
    .auto_out_w_bits_data(axi4frag_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4frag_auto_out_w_bits_strb),
    .auto_out_b_ready(axi4frag_auto_out_b_ready),
    .auto_out_b_valid(axi4frag_auto_out_b_valid),
    .auto_out_b_bits_id(axi4frag_auto_out_b_bits_id),
    .auto_out_b_bits_resp(axi4frag_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4frag_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4frag_auto_out_b_bits_echo_tl_state_source),
    .auto_out_b_bits_echo_real_last(axi4frag_auto_out_b_bits_echo_real_last),
    .auto_out_ar_ready(axi4frag_auto_out_ar_ready),
    .auto_out_ar_valid(axi4frag_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4frag_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4frag_auto_out_ar_bits_addr),
    .auto_out_ar_bits_echo_tl_state_size(axi4frag_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4frag_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_ar_bits_echo_real_last(axi4frag_auto_out_ar_bits_echo_real_last),
    .auto_out_r_ready(axi4frag_auto_out_r_ready),
    .auto_out_r_valid(axi4frag_auto_out_r_valid),
    .auto_out_r_bits_id(axi4frag_auto_out_r_bits_id),
    .auto_out_r_bits_data(axi4frag_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4frag_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4frag_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4frag_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_echo_real_last(axi4frag_auto_out_r_bits_echo_real_last)
  );
  AXI4Buffer axi4buf ( // @[Buffer.scala 58:29]
    .clock(axi4buf_clock),
    .reset(axi4buf_reset),
    .auto_in_aw_ready(axi4buf_auto_in_aw_ready),
    .auto_in_aw_valid(axi4buf_auto_in_aw_valid),
    .auto_in_aw_bits_id(axi4buf_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(axi4buf_auto_in_aw_bits_addr),
    .auto_in_aw_bits_len(axi4buf_auto_in_aw_bits_len),
    .auto_in_aw_bits_size(axi4buf_auto_in_aw_bits_size),
    .auto_in_aw_bits_burst(axi4buf_auto_in_aw_bits_burst),
    .auto_in_aw_bits_echo_tl_state_size(axi4buf_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(axi4buf_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_w_ready(axi4buf_auto_in_w_ready),
    .auto_in_w_valid(axi4buf_auto_in_w_valid),
    .auto_in_w_bits_data(axi4buf_auto_in_w_bits_data),
    .auto_in_w_bits_strb(axi4buf_auto_in_w_bits_strb),
    .auto_in_w_bits_last(axi4buf_auto_in_w_bits_last),
    .auto_in_b_ready(axi4buf_auto_in_b_ready),
    .auto_in_b_valid(axi4buf_auto_in_b_valid),
    .auto_in_b_bits_id(axi4buf_auto_in_b_bits_id),
    .auto_in_b_bits_resp(axi4buf_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(axi4buf_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(axi4buf_auto_in_b_bits_echo_tl_state_source),
    .auto_in_ar_ready(axi4buf_auto_in_ar_ready),
    .auto_in_ar_valid(axi4buf_auto_in_ar_valid),
    .auto_in_ar_bits_id(axi4buf_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(axi4buf_auto_in_ar_bits_addr),
    .auto_in_ar_bits_len(axi4buf_auto_in_ar_bits_len),
    .auto_in_ar_bits_size(axi4buf_auto_in_ar_bits_size),
    .auto_in_ar_bits_burst(axi4buf_auto_in_ar_bits_burst),
    .auto_in_ar_bits_echo_tl_state_size(axi4buf_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(axi4buf_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_r_ready(axi4buf_auto_in_r_ready),
    .auto_in_r_valid(axi4buf_auto_in_r_valid),
    .auto_in_r_bits_id(axi4buf_auto_in_r_bits_id),
    .auto_in_r_bits_data(axi4buf_auto_in_r_bits_data),
    .auto_in_r_bits_resp(axi4buf_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(axi4buf_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(axi4buf_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_last(axi4buf_auto_in_r_bits_last),
    .auto_out_aw_ready(axi4buf_auto_out_aw_ready),
    .auto_out_aw_valid(axi4buf_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4buf_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4buf_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(axi4buf_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(axi4buf_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(axi4buf_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(axi4buf_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4buf_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(axi4buf_auto_out_w_ready),
    .auto_out_w_valid(axi4buf_auto_out_w_valid),
    .auto_out_w_bits_data(axi4buf_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4buf_auto_out_w_bits_strb),
    .auto_out_w_bits_last(axi4buf_auto_out_w_bits_last),
    .auto_out_b_ready(axi4buf_auto_out_b_ready),
    .auto_out_b_valid(axi4buf_auto_out_b_valid),
    .auto_out_b_bits_id(axi4buf_auto_out_b_bits_id),
    .auto_out_b_bits_resp(axi4buf_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4buf_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4buf_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(axi4buf_auto_out_ar_ready),
    .auto_out_ar_valid(axi4buf_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4buf_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4buf_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(axi4buf_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(axi4buf_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(axi4buf_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(axi4buf_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4buf_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(axi4buf_auto_out_r_ready),
    .auto_out_r_valid(axi4buf_auto_out_r_valid),
    .auto_out_r_bits_id(axi4buf_auto_out_r_bits_id),
    .auto_out_r_bits_data(axi4buf_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4buf_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4buf_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4buf_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(axi4buf_auto_out_r_bits_last)
  );
  AXI4Buffer axi4buf_1 ( // @[Buffer.scala 58:29]
    .clock(axi4buf_1_clock),
    .reset(axi4buf_1_reset),
    .auto_in_aw_ready(axi4buf_1_auto_in_aw_ready),
    .auto_in_aw_valid(axi4buf_1_auto_in_aw_valid),
    .auto_in_aw_bits_id(axi4buf_1_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(axi4buf_1_auto_in_aw_bits_addr),
    .auto_in_aw_bits_len(axi4buf_1_auto_in_aw_bits_len),
    .auto_in_aw_bits_size(axi4buf_1_auto_in_aw_bits_size),
    .auto_in_aw_bits_burst(axi4buf_1_auto_in_aw_bits_burst),
    .auto_in_aw_bits_echo_tl_state_size(axi4buf_1_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(axi4buf_1_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_w_ready(axi4buf_1_auto_in_w_ready),
    .auto_in_w_valid(axi4buf_1_auto_in_w_valid),
    .auto_in_w_bits_data(axi4buf_1_auto_in_w_bits_data),
    .auto_in_w_bits_strb(axi4buf_1_auto_in_w_bits_strb),
    .auto_in_w_bits_last(axi4buf_1_auto_in_w_bits_last),
    .auto_in_b_ready(axi4buf_1_auto_in_b_ready),
    .auto_in_b_valid(axi4buf_1_auto_in_b_valid),
    .auto_in_b_bits_id(axi4buf_1_auto_in_b_bits_id),
    .auto_in_b_bits_resp(axi4buf_1_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(axi4buf_1_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(axi4buf_1_auto_in_b_bits_echo_tl_state_source),
    .auto_in_ar_ready(axi4buf_1_auto_in_ar_ready),
    .auto_in_ar_valid(axi4buf_1_auto_in_ar_valid),
    .auto_in_ar_bits_id(axi4buf_1_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(axi4buf_1_auto_in_ar_bits_addr),
    .auto_in_ar_bits_len(axi4buf_1_auto_in_ar_bits_len),
    .auto_in_ar_bits_size(axi4buf_1_auto_in_ar_bits_size),
    .auto_in_ar_bits_burst(axi4buf_1_auto_in_ar_bits_burst),
    .auto_in_ar_bits_echo_tl_state_size(axi4buf_1_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(axi4buf_1_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_r_ready(axi4buf_1_auto_in_r_ready),
    .auto_in_r_valid(axi4buf_1_auto_in_r_valid),
    .auto_in_r_bits_id(axi4buf_1_auto_in_r_bits_id),
    .auto_in_r_bits_data(axi4buf_1_auto_in_r_bits_data),
    .auto_in_r_bits_resp(axi4buf_1_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(axi4buf_1_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(axi4buf_1_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_last(axi4buf_1_auto_in_r_bits_last),
    .auto_out_aw_ready(axi4buf_1_auto_out_aw_ready),
    .auto_out_aw_valid(axi4buf_1_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4buf_1_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4buf_1_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(axi4buf_1_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(axi4buf_1_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(axi4buf_1_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(axi4buf_1_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4buf_1_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(axi4buf_1_auto_out_w_ready),
    .auto_out_w_valid(axi4buf_1_auto_out_w_valid),
    .auto_out_w_bits_data(axi4buf_1_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4buf_1_auto_out_w_bits_strb),
    .auto_out_w_bits_last(axi4buf_1_auto_out_w_bits_last),
    .auto_out_b_ready(axi4buf_1_auto_out_b_ready),
    .auto_out_b_valid(axi4buf_1_auto_out_b_valid),
    .auto_out_b_bits_id(axi4buf_1_auto_out_b_bits_id),
    .auto_out_b_bits_resp(axi4buf_1_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4buf_1_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4buf_1_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(axi4buf_1_auto_out_ar_ready),
    .auto_out_ar_valid(axi4buf_1_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4buf_1_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4buf_1_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(axi4buf_1_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(axi4buf_1_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(axi4buf_1_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(axi4buf_1_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4buf_1_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(axi4buf_1_auto_out_r_ready),
    .auto_out_r_valid(axi4buf_1_auto_out_r_valid),
    .auto_out_r_bits_id(axi4buf_1_auto_out_r_bits_id),
    .auto_out_r_bits_data(axi4buf_1_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4buf_1_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4buf_1_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4buf_1_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(axi4buf_1_auto_out_r_bits_last)
  );
  AXI4Delayer axi4delay ( // @[Delayer.scala 78:31]
    .clock(axi4delay_clock),
    .reset(axi4delay_reset),
    .auto_in_aw_ready(axi4delay_auto_in_aw_ready),
    .auto_in_aw_valid(axi4delay_auto_in_aw_valid),
    .auto_in_aw_bits_id(axi4delay_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(axi4delay_auto_in_aw_bits_addr),
    .auto_in_aw_bits_len(axi4delay_auto_in_aw_bits_len),
    .auto_in_aw_bits_size(axi4delay_auto_in_aw_bits_size),
    .auto_in_aw_bits_burst(axi4delay_auto_in_aw_bits_burst),
    .auto_in_aw_bits_echo_tl_state_size(axi4delay_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(axi4delay_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_w_ready(axi4delay_auto_in_w_ready),
    .auto_in_w_valid(axi4delay_auto_in_w_valid),
    .auto_in_w_bits_data(axi4delay_auto_in_w_bits_data),
    .auto_in_w_bits_strb(axi4delay_auto_in_w_bits_strb),
    .auto_in_w_bits_last(axi4delay_auto_in_w_bits_last),
    .auto_in_b_ready(axi4delay_auto_in_b_ready),
    .auto_in_b_valid(axi4delay_auto_in_b_valid),
    .auto_in_b_bits_id(axi4delay_auto_in_b_bits_id),
    .auto_in_b_bits_resp(axi4delay_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(axi4delay_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(axi4delay_auto_in_b_bits_echo_tl_state_source),
    .auto_in_ar_ready(axi4delay_auto_in_ar_ready),
    .auto_in_ar_valid(axi4delay_auto_in_ar_valid),
    .auto_in_ar_bits_id(axi4delay_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(axi4delay_auto_in_ar_bits_addr),
    .auto_in_ar_bits_len(axi4delay_auto_in_ar_bits_len),
    .auto_in_ar_bits_size(axi4delay_auto_in_ar_bits_size),
    .auto_in_ar_bits_burst(axi4delay_auto_in_ar_bits_burst),
    .auto_in_ar_bits_echo_tl_state_size(axi4delay_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(axi4delay_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_r_ready(axi4delay_auto_in_r_ready),
    .auto_in_r_valid(axi4delay_auto_in_r_valid),
    .auto_in_r_bits_id(axi4delay_auto_in_r_bits_id),
    .auto_in_r_bits_data(axi4delay_auto_in_r_bits_data),
    .auto_in_r_bits_resp(axi4delay_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(axi4delay_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(axi4delay_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_last(axi4delay_auto_in_r_bits_last),
    .auto_out_aw_ready(axi4delay_auto_out_aw_ready),
    .auto_out_aw_valid(axi4delay_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4delay_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4delay_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(axi4delay_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(axi4delay_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(axi4delay_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(axi4delay_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4delay_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(axi4delay_auto_out_w_ready),
    .auto_out_w_valid(axi4delay_auto_out_w_valid),
    .auto_out_w_bits_data(axi4delay_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4delay_auto_out_w_bits_strb),
    .auto_out_w_bits_last(axi4delay_auto_out_w_bits_last),
    .auto_out_b_ready(axi4delay_auto_out_b_ready),
    .auto_out_b_valid(axi4delay_auto_out_b_valid),
    .auto_out_b_bits_id(axi4delay_auto_out_b_bits_id),
    .auto_out_b_bits_resp(axi4delay_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4delay_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4delay_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(axi4delay_auto_out_ar_ready),
    .auto_out_ar_valid(axi4delay_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4delay_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4delay_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(axi4delay_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(axi4delay_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(axi4delay_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(axi4delay_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4delay_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(axi4delay_auto_out_r_ready),
    .auto_out_r_valid(axi4delay_auto_out_r_valid),
    .auto_out_r_bits_id(axi4delay_auto_out_r_bits_id),
    .auto_out_r_bits_data(axi4delay_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4delay_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4delay_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4delay_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(axi4delay_auto_out_r_bits_last)
  );
  TLFuzzer masters ( // @[Xbar.scala 306:48]
    .clock(masters_clock),
    .reset(masters_reset),
    .auto_out_a_ready(masters_auto_out_a_ready),
    .auto_out_a_valid(masters_auto_out_a_valid),
    .auto_out_a_bits_opcode(masters_auto_out_a_bits_opcode),
    .auto_out_a_bits_size(masters_auto_out_a_bits_size),
    .auto_out_a_bits_source(masters_auto_out_a_bits_source),
    .auto_out_a_bits_address(masters_auto_out_a_bits_address),
    .auto_out_a_bits_mask(masters_auto_out_a_bits_mask),
    .auto_out_a_bits_data(masters_auto_out_a_bits_data),
    .auto_out_d_valid(masters_auto_out_d_valid),
    .auto_out_d_bits_opcode(masters_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(masters_auto_out_d_bits_size),
    .auto_out_d_bits_source(masters_auto_out_d_bits_source),
    .io_finished(masters_io_finished)
  );
  TLFuzzer_1 masters_1 ( // @[Xbar.scala 306:48]
    .clock(masters_1_clock),
    .reset(masters_1_reset),
    .auto_out_a_ready(masters_1_auto_out_a_ready),
    .auto_out_a_valid(masters_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(masters_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_size(masters_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(masters_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(masters_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(masters_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(masters_1_auto_out_a_bits_data),
    .auto_out_d_valid(masters_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(masters_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(masters_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(masters_1_auto_out_d_bits_source),
    .io_finished(masters_1_io_finished)
  );
  AXI4Delayer axi4delay_1 ( // @[Delayer.scala 78:31]
    .clock(axi4delay_1_clock),
    .reset(axi4delay_1_reset),
    .auto_in_aw_ready(axi4delay_1_auto_in_aw_ready),
    .auto_in_aw_valid(axi4delay_1_auto_in_aw_valid),
    .auto_in_aw_bits_id(axi4delay_1_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(axi4delay_1_auto_in_aw_bits_addr),
    .auto_in_aw_bits_len(axi4delay_1_auto_in_aw_bits_len),
    .auto_in_aw_bits_size(axi4delay_1_auto_in_aw_bits_size),
    .auto_in_aw_bits_burst(axi4delay_1_auto_in_aw_bits_burst),
    .auto_in_aw_bits_echo_tl_state_size(axi4delay_1_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(axi4delay_1_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_w_ready(axi4delay_1_auto_in_w_ready),
    .auto_in_w_valid(axi4delay_1_auto_in_w_valid),
    .auto_in_w_bits_data(axi4delay_1_auto_in_w_bits_data),
    .auto_in_w_bits_strb(axi4delay_1_auto_in_w_bits_strb),
    .auto_in_w_bits_last(axi4delay_1_auto_in_w_bits_last),
    .auto_in_b_ready(axi4delay_1_auto_in_b_ready),
    .auto_in_b_valid(axi4delay_1_auto_in_b_valid),
    .auto_in_b_bits_id(axi4delay_1_auto_in_b_bits_id),
    .auto_in_b_bits_resp(axi4delay_1_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(axi4delay_1_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(axi4delay_1_auto_in_b_bits_echo_tl_state_source),
    .auto_in_ar_ready(axi4delay_1_auto_in_ar_ready),
    .auto_in_ar_valid(axi4delay_1_auto_in_ar_valid),
    .auto_in_ar_bits_id(axi4delay_1_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(axi4delay_1_auto_in_ar_bits_addr),
    .auto_in_ar_bits_len(axi4delay_1_auto_in_ar_bits_len),
    .auto_in_ar_bits_size(axi4delay_1_auto_in_ar_bits_size),
    .auto_in_ar_bits_burst(axi4delay_1_auto_in_ar_bits_burst),
    .auto_in_ar_bits_echo_tl_state_size(axi4delay_1_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(axi4delay_1_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_r_ready(axi4delay_1_auto_in_r_ready),
    .auto_in_r_valid(axi4delay_1_auto_in_r_valid),
    .auto_in_r_bits_id(axi4delay_1_auto_in_r_bits_id),
    .auto_in_r_bits_data(axi4delay_1_auto_in_r_bits_data),
    .auto_in_r_bits_resp(axi4delay_1_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(axi4delay_1_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(axi4delay_1_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_last(axi4delay_1_auto_in_r_bits_last),
    .auto_out_aw_ready(axi4delay_1_auto_out_aw_ready),
    .auto_out_aw_valid(axi4delay_1_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4delay_1_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4delay_1_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(axi4delay_1_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(axi4delay_1_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(axi4delay_1_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(axi4delay_1_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4delay_1_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(axi4delay_1_auto_out_w_ready),
    .auto_out_w_valid(axi4delay_1_auto_out_w_valid),
    .auto_out_w_bits_data(axi4delay_1_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4delay_1_auto_out_w_bits_strb),
    .auto_out_w_bits_last(axi4delay_1_auto_out_w_bits_last),
    .auto_out_b_ready(axi4delay_1_auto_out_b_ready),
    .auto_out_b_valid(axi4delay_1_auto_out_b_valid),
    .auto_out_b_bits_id(axi4delay_1_auto_out_b_bits_id),
    .auto_out_b_bits_resp(axi4delay_1_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4delay_1_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4delay_1_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(axi4delay_1_auto_out_ar_ready),
    .auto_out_ar_valid(axi4delay_1_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4delay_1_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4delay_1_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(axi4delay_1_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(axi4delay_1_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(axi4delay_1_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(axi4delay_1_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4delay_1_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(axi4delay_1_auto_out_r_ready),
    .auto_out_r_valid(axi4delay_1_auto_out_r_valid),
    .auto_out_r_bits_id(axi4delay_1_auto_out_r_bits_id),
    .auto_out_r_bits_data(axi4delay_1_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4delay_1_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4delay_1_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4delay_1_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(axi4delay_1_auto_out_r_bits_last)
  );
  AXI4Deinterleaver axi4deint ( // @[Deinterleaver.scala 140:31]
    .clock(axi4deint_clock),
    .reset(axi4deint_reset),
    .auto_in_aw_ready(axi4deint_auto_in_aw_ready),
    .auto_in_aw_valid(axi4deint_auto_in_aw_valid),
    .auto_in_aw_bits_id(axi4deint_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(axi4deint_auto_in_aw_bits_addr),
    .auto_in_aw_bits_len(axi4deint_auto_in_aw_bits_len),
    .auto_in_aw_bits_size(axi4deint_auto_in_aw_bits_size),
    .auto_in_aw_bits_burst(axi4deint_auto_in_aw_bits_burst),
    .auto_in_aw_bits_echo_tl_state_size(axi4deint_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(axi4deint_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_w_ready(axi4deint_auto_in_w_ready),
    .auto_in_w_valid(axi4deint_auto_in_w_valid),
    .auto_in_w_bits_data(axi4deint_auto_in_w_bits_data),
    .auto_in_w_bits_strb(axi4deint_auto_in_w_bits_strb),
    .auto_in_w_bits_last(axi4deint_auto_in_w_bits_last),
    .auto_in_b_ready(axi4deint_auto_in_b_ready),
    .auto_in_b_valid(axi4deint_auto_in_b_valid),
    .auto_in_b_bits_resp(axi4deint_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(axi4deint_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(axi4deint_auto_in_b_bits_echo_tl_state_source),
    .auto_in_ar_ready(axi4deint_auto_in_ar_ready),
    .auto_in_ar_valid(axi4deint_auto_in_ar_valid),
    .auto_in_ar_bits_id(axi4deint_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(axi4deint_auto_in_ar_bits_addr),
    .auto_in_ar_bits_len(axi4deint_auto_in_ar_bits_len),
    .auto_in_ar_bits_size(axi4deint_auto_in_ar_bits_size),
    .auto_in_ar_bits_burst(axi4deint_auto_in_ar_bits_burst),
    .auto_in_ar_bits_echo_tl_state_size(axi4deint_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(axi4deint_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_r_ready(axi4deint_auto_in_r_ready),
    .auto_in_r_valid(axi4deint_auto_in_r_valid),
    .auto_in_r_bits_data(axi4deint_auto_in_r_bits_data),
    .auto_in_r_bits_resp(axi4deint_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(axi4deint_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(axi4deint_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_last(axi4deint_auto_in_r_bits_last),
    .auto_out_aw_ready(axi4deint_auto_out_aw_ready),
    .auto_out_aw_valid(axi4deint_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4deint_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4deint_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(axi4deint_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(axi4deint_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(axi4deint_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(axi4deint_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4deint_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(axi4deint_auto_out_w_ready),
    .auto_out_w_valid(axi4deint_auto_out_w_valid),
    .auto_out_w_bits_data(axi4deint_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4deint_auto_out_w_bits_strb),
    .auto_out_w_bits_last(axi4deint_auto_out_w_bits_last),
    .auto_out_b_ready(axi4deint_auto_out_b_ready),
    .auto_out_b_valid(axi4deint_auto_out_b_valid),
    .auto_out_b_bits_resp(axi4deint_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4deint_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4deint_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(axi4deint_auto_out_ar_ready),
    .auto_out_ar_valid(axi4deint_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4deint_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4deint_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(axi4deint_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(axi4deint_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(axi4deint_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(axi4deint_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4deint_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(axi4deint_auto_out_r_ready),
    .auto_out_r_valid(axi4deint_auto_out_r_valid),
    .auto_out_r_bits_data(axi4deint_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4deint_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4deint_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4deint_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(axi4deint_auto_out_r_bits_last)
  );
  TLToAXI4 tl2axi4 ( // @[ToAXI4.scala 283:29]
    .clock(tl2axi4_clock),
    .reset(tl2axi4_reset),
    .auto_in_a_ready(tl2axi4_auto_in_a_ready),
    .auto_in_a_valid(tl2axi4_auto_in_a_valid),
    .auto_in_a_bits_opcode(tl2axi4_auto_in_a_bits_opcode),
    .auto_in_a_bits_size(tl2axi4_auto_in_a_bits_size),
    .auto_in_a_bits_source(tl2axi4_auto_in_a_bits_source),
    .auto_in_a_bits_address(tl2axi4_auto_in_a_bits_address),
    .auto_in_a_bits_mask(tl2axi4_auto_in_a_bits_mask),
    .auto_in_a_bits_data(tl2axi4_auto_in_a_bits_data),
    .auto_in_d_ready(tl2axi4_auto_in_d_ready),
    .auto_in_d_valid(tl2axi4_auto_in_d_valid),
    .auto_in_d_bits_opcode(tl2axi4_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(tl2axi4_auto_in_d_bits_size),
    .auto_in_d_bits_source(tl2axi4_auto_in_d_bits_source),
    .auto_in_d_bits_denied(tl2axi4_auto_in_d_bits_denied),
    .auto_in_d_bits_data(tl2axi4_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(tl2axi4_auto_in_d_bits_corrupt),
    .auto_out_aw_ready(tl2axi4_auto_out_aw_ready),
    .auto_out_aw_valid(tl2axi4_auto_out_aw_valid),
    .auto_out_aw_bits_id(tl2axi4_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(tl2axi4_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(tl2axi4_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(tl2axi4_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(tl2axi4_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(tl2axi4_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(tl2axi4_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(tl2axi4_auto_out_w_ready),
    .auto_out_w_valid(tl2axi4_auto_out_w_valid),
    .auto_out_w_bits_data(tl2axi4_auto_out_w_bits_data),
    .auto_out_w_bits_strb(tl2axi4_auto_out_w_bits_strb),
    .auto_out_w_bits_last(tl2axi4_auto_out_w_bits_last),
    .auto_out_b_ready(tl2axi4_auto_out_b_ready),
    .auto_out_b_valid(tl2axi4_auto_out_b_valid),
    .auto_out_b_bits_resp(tl2axi4_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(tl2axi4_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(tl2axi4_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(tl2axi4_auto_out_ar_ready),
    .auto_out_ar_valid(tl2axi4_auto_out_ar_valid),
    .auto_out_ar_bits_id(tl2axi4_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(tl2axi4_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(tl2axi4_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(tl2axi4_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(tl2axi4_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(tl2axi4_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(tl2axi4_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(tl2axi4_auto_out_r_ready),
    .auto_out_r_valid(tl2axi4_auto_out_r_valid),
    .auto_out_r_bits_data(tl2axi4_auto_out_r_bits_data),
    .auto_out_r_bits_resp(tl2axi4_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(tl2axi4_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(tl2axi4_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(tl2axi4_auto_out_r_bits_last)
  );
  TLFilter filter ( // @[Filter.scala 164:28]
    .auto_in_a_ready(filter_auto_in_a_ready),
    .auto_in_a_valid(filter_auto_in_a_valid),
    .auto_in_a_bits_opcode(filter_auto_in_a_bits_opcode),
    .auto_in_a_bits_size(filter_auto_in_a_bits_size),
    .auto_in_a_bits_source(filter_auto_in_a_bits_source),
    .auto_in_a_bits_address(filter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(filter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(filter_auto_in_a_bits_data),
    .auto_in_d_ready(filter_auto_in_d_ready),
    .auto_in_d_valid(filter_auto_in_d_valid),
    .auto_in_d_bits_opcode(filter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(filter_auto_in_d_bits_size),
    .auto_in_d_bits_source(filter_auto_in_d_bits_source),
    .auto_in_d_bits_denied(filter_auto_in_d_bits_denied),
    .auto_in_d_bits_data(filter_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(filter_auto_in_d_bits_corrupt),
    .auto_out_a_ready(filter_auto_out_a_ready),
    .auto_out_a_valid(filter_auto_out_a_valid),
    .auto_out_a_bits_opcode(filter_auto_out_a_bits_opcode),
    .auto_out_a_bits_size(filter_auto_out_a_bits_size),
    .auto_out_a_bits_source(filter_auto_out_a_bits_source),
    .auto_out_a_bits_address(filter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(filter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(filter_auto_out_a_bits_data),
    .auto_out_d_ready(filter_auto_out_d_ready),
    .auto_out_d_valid(filter_auto_out_d_valid),
    .auto_out_d_bits_opcode(filter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(filter_auto_out_d_bits_size),
    .auto_out_d_bits_source(filter_auto_out_d_bits_source),
    .auto_out_d_bits_denied(filter_auto_out_d_bits_denied),
    .auto_out_d_bits_data(filter_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(filter_auto_out_d_bits_corrupt)
  );
  TLRAMModel model ( // @[RAMModel.scala 340:27]
    .clock(model_clock),
    .reset(model_reset),
    .auto_in_a_ready(model_auto_in_a_ready),
    .auto_in_a_valid(model_auto_in_a_valid),
    .auto_in_a_bits_opcode(model_auto_in_a_bits_opcode),
    .auto_in_a_bits_size(model_auto_in_a_bits_size),
    .auto_in_a_bits_source(model_auto_in_a_bits_source),
    .auto_in_a_bits_address(model_auto_in_a_bits_address),
    .auto_in_a_bits_mask(model_auto_in_a_bits_mask),
    .auto_in_a_bits_data(model_auto_in_a_bits_data),
    .auto_in_d_valid(model_auto_in_d_valid),
    .auto_in_d_bits_opcode(model_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(model_auto_in_d_bits_size),
    .auto_in_d_bits_source(model_auto_in_d_bits_source),
    .auto_out_a_ready(model_auto_out_a_ready),
    .auto_out_a_valid(model_auto_out_a_valid),
    .auto_out_a_bits_opcode(model_auto_out_a_bits_opcode),
    .auto_out_a_bits_size(model_auto_out_a_bits_size),
    .auto_out_a_bits_source(model_auto_out_a_bits_source),
    .auto_out_a_bits_address(model_auto_out_a_bits_address),
    .auto_out_a_bits_mask(model_auto_out_a_bits_mask),
    .auto_out_a_bits_data(model_auto_out_a_bits_data),
    .auto_out_d_ready(model_auto_out_d_ready),
    .auto_out_d_valid(model_auto_out_d_valid),
    .auto_out_d_bits_opcode(model_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(model_auto_out_d_bits_size),
    .auto_out_d_bits_source(model_auto_out_d_bits_source),
    .auto_out_d_bits_denied(model_auto_out_d_bits_denied),
    .auto_out_d_bits_data(model_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(model_auto_out_d_bits_corrupt)
  );
  AXI4Delayer axi4delay_2 ( // @[Delayer.scala 78:31]
    .clock(axi4delay_2_clock),
    .reset(axi4delay_2_reset),
    .auto_in_aw_ready(axi4delay_2_auto_in_aw_ready),
    .auto_in_aw_valid(axi4delay_2_auto_in_aw_valid),
    .auto_in_aw_bits_id(axi4delay_2_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(axi4delay_2_auto_in_aw_bits_addr),
    .auto_in_aw_bits_len(axi4delay_2_auto_in_aw_bits_len),
    .auto_in_aw_bits_size(axi4delay_2_auto_in_aw_bits_size),
    .auto_in_aw_bits_burst(axi4delay_2_auto_in_aw_bits_burst),
    .auto_in_aw_bits_echo_tl_state_size(axi4delay_2_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(axi4delay_2_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_w_ready(axi4delay_2_auto_in_w_ready),
    .auto_in_w_valid(axi4delay_2_auto_in_w_valid),
    .auto_in_w_bits_data(axi4delay_2_auto_in_w_bits_data),
    .auto_in_w_bits_strb(axi4delay_2_auto_in_w_bits_strb),
    .auto_in_w_bits_last(axi4delay_2_auto_in_w_bits_last),
    .auto_in_b_ready(axi4delay_2_auto_in_b_ready),
    .auto_in_b_valid(axi4delay_2_auto_in_b_valid),
    .auto_in_b_bits_id(axi4delay_2_auto_in_b_bits_id),
    .auto_in_b_bits_resp(axi4delay_2_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(axi4delay_2_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(axi4delay_2_auto_in_b_bits_echo_tl_state_source),
    .auto_in_ar_ready(axi4delay_2_auto_in_ar_ready),
    .auto_in_ar_valid(axi4delay_2_auto_in_ar_valid),
    .auto_in_ar_bits_id(axi4delay_2_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(axi4delay_2_auto_in_ar_bits_addr),
    .auto_in_ar_bits_len(axi4delay_2_auto_in_ar_bits_len),
    .auto_in_ar_bits_size(axi4delay_2_auto_in_ar_bits_size),
    .auto_in_ar_bits_burst(axi4delay_2_auto_in_ar_bits_burst),
    .auto_in_ar_bits_echo_tl_state_size(axi4delay_2_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(axi4delay_2_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_r_ready(axi4delay_2_auto_in_r_ready),
    .auto_in_r_valid(axi4delay_2_auto_in_r_valid),
    .auto_in_r_bits_id(axi4delay_2_auto_in_r_bits_id),
    .auto_in_r_bits_data(axi4delay_2_auto_in_r_bits_data),
    .auto_in_r_bits_resp(axi4delay_2_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(axi4delay_2_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(axi4delay_2_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_last(axi4delay_2_auto_in_r_bits_last),
    .auto_out_aw_ready(axi4delay_2_auto_out_aw_ready),
    .auto_out_aw_valid(axi4delay_2_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4delay_2_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4delay_2_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(axi4delay_2_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(axi4delay_2_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(axi4delay_2_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(axi4delay_2_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4delay_2_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(axi4delay_2_auto_out_w_ready),
    .auto_out_w_valid(axi4delay_2_auto_out_w_valid),
    .auto_out_w_bits_data(axi4delay_2_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4delay_2_auto_out_w_bits_strb),
    .auto_out_w_bits_last(axi4delay_2_auto_out_w_bits_last),
    .auto_out_b_ready(axi4delay_2_auto_out_b_ready),
    .auto_out_b_valid(axi4delay_2_auto_out_b_valid),
    .auto_out_b_bits_id(axi4delay_2_auto_out_b_bits_id),
    .auto_out_b_bits_resp(axi4delay_2_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4delay_2_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4delay_2_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(axi4delay_2_auto_out_ar_ready),
    .auto_out_ar_valid(axi4delay_2_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4delay_2_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4delay_2_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(axi4delay_2_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(axi4delay_2_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(axi4delay_2_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(axi4delay_2_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4delay_2_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(axi4delay_2_auto_out_r_ready),
    .auto_out_r_valid(axi4delay_2_auto_out_r_valid),
    .auto_out_r_bits_id(axi4delay_2_auto_out_r_bits_id),
    .auto_out_r_bits_data(axi4delay_2_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4delay_2_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4delay_2_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4delay_2_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(axi4delay_2_auto_out_r_bits_last)
  );
  AXI4Deinterleaver axi4deint_1 ( // @[Deinterleaver.scala 140:31]
    .clock(axi4deint_1_clock),
    .reset(axi4deint_1_reset),
    .auto_in_aw_ready(axi4deint_1_auto_in_aw_ready),
    .auto_in_aw_valid(axi4deint_1_auto_in_aw_valid),
    .auto_in_aw_bits_id(axi4deint_1_auto_in_aw_bits_id),
    .auto_in_aw_bits_addr(axi4deint_1_auto_in_aw_bits_addr),
    .auto_in_aw_bits_len(axi4deint_1_auto_in_aw_bits_len),
    .auto_in_aw_bits_size(axi4deint_1_auto_in_aw_bits_size),
    .auto_in_aw_bits_burst(axi4deint_1_auto_in_aw_bits_burst),
    .auto_in_aw_bits_echo_tl_state_size(axi4deint_1_auto_in_aw_bits_echo_tl_state_size),
    .auto_in_aw_bits_echo_tl_state_source(axi4deint_1_auto_in_aw_bits_echo_tl_state_source),
    .auto_in_w_ready(axi4deint_1_auto_in_w_ready),
    .auto_in_w_valid(axi4deint_1_auto_in_w_valid),
    .auto_in_w_bits_data(axi4deint_1_auto_in_w_bits_data),
    .auto_in_w_bits_strb(axi4deint_1_auto_in_w_bits_strb),
    .auto_in_w_bits_last(axi4deint_1_auto_in_w_bits_last),
    .auto_in_b_ready(axi4deint_1_auto_in_b_ready),
    .auto_in_b_valid(axi4deint_1_auto_in_b_valid),
    .auto_in_b_bits_resp(axi4deint_1_auto_in_b_bits_resp),
    .auto_in_b_bits_echo_tl_state_size(axi4deint_1_auto_in_b_bits_echo_tl_state_size),
    .auto_in_b_bits_echo_tl_state_source(axi4deint_1_auto_in_b_bits_echo_tl_state_source),
    .auto_in_ar_ready(axi4deint_1_auto_in_ar_ready),
    .auto_in_ar_valid(axi4deint_1_auto_in_ar_valid),
    .auto_in_ar_bits_id(axi4deint_1_auto_in_ar_bits_id),
    .auto_in_ar_bits_addr(axi4deint_1_auto_in_ar_bits_addr),
    .auto_in_ar_bits_len(axi4deint_1_auto_in_ar_bits_len),
    .auto_in_ar_bits_size(axi4deint_1_auto_in_ar_bits_size),
    .auto_in_ar_bits_burst(axi4deint_1_auto_in_ar_bits_burst),
    .auto_in_ar_bits_echo_tl_state_size(axi4deint_1_auto_in_ar_bits_echo_tl_state_size),
    .auto_in_ar_bits_echo_tl_state_source(axi4deint_1_auto_in_ar_bits_echo_tl_state_source),
    .auto_in_r_ready(axi4deint_1_auto_in_r_ready),
    .auto_in_r_valid(axi4deint_1_auto_in_r_valid),
    .auto_in_r_bits_data(axi4deint_1_auto_in_r_bits_data),
    .auto_in_r_bits_resp(axi4deint_1_auto_in_r_bits_resp),
    .auto_in_r_bits_echo_tl_state_size(axi4deint_1_auto_in_r_bits_echo_tl_state_size),
    .auto_in_r_bits_echo_tl_state_source(axi4deint_1_auto_in_r_bits_echo_tl_state_source),
    .auto_in_r_bits_last(axi4deint_1_auto_in_r_bits_last),
    .auto_out_aw_ready(axi4deint_1_auto_out_aw_ready),
    .auto_out_aw_valid(axi4deint_1_auto_out_aw_valid),
    .auto_out_aw_bits_id(axi4deint_1_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(axi4deint_1_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(axi4deint_1_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(axi4deint_1_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(axi4deint_1_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(axi4deint_1_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(axi4deint_1_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(axi4deint_1_auto_out_w_ready),
    .auto_out_w_valid(axi4deint_1_auto_out_w_valid),
    .auto_out_w_bits_data(axi4deint_1_auto_out_w_bits_data),
    .auto_out_w_bits_strb(axi4deint_1_auto_out_w_bits_strb),
    .auto_out_w_bits_last(axi4deint_1_auto_out_w_bits_last),
    .auto_out_b_ready(axi4deint_1_auto_out_b_ready),
    .auto_out_b_valid(axi4deint_1_auto_out_b_valid),
    .auto_out_b_bits_resp(axi4deint_1_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(axi4deint_1_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(axi4deint_1_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(axi4deint_1_auto_out_ar_ready),
    .auto_out_ar_valid(axi4deint_1_auto_out_ar_valid),
    .auto_out_ar_bits_id(axi4deint_1_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(axi4deint_1_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(axi4deint_1_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(axi4deint_1_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(axi4deint_1_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(axi4deint_1_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(axi4deint_1_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(axi4deint_1_auto_out_r_ready),
    .auto_out_r_valid(axi4deint_1_auto_out_r_valid),
    .auto_out_r_bits_data(axi4deint_1_auto_out_r_bits_data),
    .auto_out_r_bits_resp(axi4deint_1_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(axi4deint_1_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(axi4deint_1_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(axi4deint_1_auto_out_r_bits_last)
  );
  TLToAXI4 tl2axi4_1 ( // @[ToAXI4.scala 283:29]
    .clock(tl2axi4_1_clock),
    .reset(tl2axi4_1_reset),
    .auto_in_a_ready(tl2axi4_1_auto_in_a_ready),
    .auto_in_a_valid(tl2axi4_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(tl2axi4_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_size(tl2axi4_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(tl2axi4_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(tl2axi4_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(tl2axi4_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(tl2axi4_1_auto_in_a_bits_data),
    .auto_in_d_ready(tl2axi4_1_auto_in_d_ready),
    .auto_in_d_valid(tl2axi4_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(tl2axi4_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(tl2axi4_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(tl2axi4_1_auto_in_d_bits_source),
    .auto_in_d_bits_denied(tl2axi4_1_auto_in_d_bits_denied),
    .auto_in_d_bits_data(tl2axi4_1_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(tl2axi4_1_auto_in_d_bits_corrupt),
    .auto_out_aw_ready(tl2axi4_1_auto_out_aw_ready),
    .auto_out_aw_valid(tl2axi4_1_auto_out_aw_valid),
    .auto_out_aw_bits_id(tl2axi4_1_auto_out_aw_bits_id),
    .auto_out_aw_bits_addr(tl2axi4_1_auto_out_aw_bits_addr),
    .auto_out_aw_bits_len(tl2axi4_1_auto_out_aw_bits_len),
    .auto_out_aw_bits_size(tl2axi4_1_auto_out_aw_bits_size),
    .auto_out_aw_bits_burst(tl2axi4_1_auto_out_aw_bits_burst),
    .auto_out_aw_bits_echo_tl_state_size(tl2axi4_1_auto_out_aw_bits_echo_tl_state_size),
    .auto_out_aw_bits_echo_tl_state_source(tl2axi4_1_auto_out_aw_bits_echo_tl_state_source),
    .auto_out_w_ready(tl2axi4_1_auto_out_w_ready),
    .auto_out_w_valid(tl2axi4_1_auto_out_w_valid),
    .auto_out_w_bits_data(tl2axi4_1_auto_out_w_bits_data),
    .auto_out_w_bits_strb(tl2axi4_1_auto_out_w_bits_strb),
    .auto_out_w_bits_last(tl2axi4_1_auto_out_w_bits_last),
    .auto_out_b_ready(tl2axi4_1_auto_out_b_ready),
    .auto_out_b_valid(tl2axi4_1_auto_out_b_valid),
    .auto_out_b_bits_resp(tl2axi4_1_auto_out_b_bits_resp),
    .auto_out_b_bits_echo_tl_state_size(tl2axi4_1_auto_out_b_bits_echo_tl_state_size),
    .auto_out_b_bits_echo_tl_state_source(tl2axi4_1_auto_out_b_bits_echo_tl_state_source),
    .auto_out_ar_ready(tl2axi4_1_auto_out_ar_ready),
    .auto_out_ar_valid(tl2axi4_1_auto_out_ar_valid),
    .auto_out_ar_bits_id(tl2axi4_1_auto_out_ar_bits_id),
    .auto_out_ar_bits_addr(tl2axi4_1_auto_out_ar_bits_addr),
    .auto_out_ar_bits_len(tl2axi4_1_auto_out_ar_bits_len),
    .auto_out_ar_bits_size(tl2axi4_1_auto_out_ar_bits_size),
    .auto_out_ar_bits_burst(tl2axi4_1_auto_out_ar_bits_burst),
    .auto_out_ar_bits_echo_tl_state_size(tl2axi4_1_auto_out_ar_bits_echo_tl_state_size),
    .auto_out_ar_bits_echo_tl_state_source(tl2axi4_1_auto_out_ar_bits_echo_tl_state_source),
    .auto_out_r_ready(tl2axi4_1_auto_out_r_ready),
    .auto_out_r_valid(tl2axi4_1_auto_out_r_valid),
    .auto_out_r_bits_data(tl2axi4_1_auto_out_r_bits_data),
    .auto_out_r_bits_resp(tl2axi4_1_auto_out_r_bits_resp),
    .auto_out_r_bits_echo_tl_state_size(tl2axi4_1_auto_out_r_bits_echo_tl_state_size),
    .auto_out_r_bits_echo_tl_state_source(tl2axi4_1_auto_out_r_bits_echo_tl_state_source),
    .auto_out_r_bits_last(tl2axi4_1_auto_out_r_bits_last)
  );
  TLFilter_1 filter_1 ( // @[Filter.scala 164:28]
    .auto_in_a_ready(filter_1_auto_in_a_ready),
    .auto_in_a_valid(filter_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(filter_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_size(filter_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(filter_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(filter_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(filter_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(filter_1_auto_in_a_bits_data),
    .auto_in_d_ready(filter_1_auto_in_d_ready),
    .auto_in_d_valid(filter_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(filter_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(filter_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(filter_1_auto_in_d_bits_source),
    .auto_in_d_bits_denied(filter_1_auto_in_d_bits_denied),
    .auto_in_d_bits_data(filter_1_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(filter_1_auto_in_d_bits_corrupt),
    .auto_out_a_ready(filter_1_auto_out_a_ready),
    .auto_out_a_valid(filter_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(filter_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_size(filter_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(filter_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(filter_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(filter_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(filter_1_auto_out_a_bits_data),
    .auto_out_d_ready(filter_1_auto_out_d_ready),
    .auto_out_d_valid(filter_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(filter_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(filter_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(filter_1_auto_out_d_bits_source),
    .auto_out_d_bits_denied(filter_1_auto_out_d_bits_denied),
    .auto_out_d_bits_data(filter_1_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(filter_1_auto_out_d_bits_corrupt)
  );
  TLRAMModel_1 model_1 ( // @[RAMModel.scala 340:27]
    .clock(model_1_clock),
    .reset(model_1_reset),
    .auto_in_a_ready(model_1_auto_in_a_ready),
    .auto_in_a_valid(model_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(model_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_size(model_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(model_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(model_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(model_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(model_1_auto_in_a_bits_data),
    .auto_in_d_valid(model_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(model_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(model_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(model_1_auto_in_d_bits_source),
    .auto_out_a_ready(model_1_auto_out_a_ready),
    .auto_out_a_valid(model_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(model_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_size(model_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(model_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(model_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(model_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(model_1_auto_out_a_bits_data),
    .auto_out_d_ready(model_1_auto_out_d_ready),
    .auto_out_d_valid(model_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(model_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(model_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(model_1_auto_out_d_bits_source),
    .auto_out_d_bits_denied(model_1_auto_out_d_bits_denied),
    .auto_out_d_bits_data(model_1_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(model_1_auto_out_d_bits_corrupt)
  );
  assign io_finished = masters_io_finished | masters_1_io_finished; // @[Xbar.scala 316:63]
  assign axi4xbar_clock = clock;
  assign axi4xbar_reset = reset;
  assign axi4xbar_auto_in_1_aw_valid = axi4delay_2_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_aw_bits_id = axi4delay_2_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_aw_bits_addr = axi4delay_2_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_aw_bits_len = axi4delay_2_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_aw_bits_size = axi4delay_2_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_aw_bits_burst = axi4delay_2_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_aw_bits_echo_tl_state_size = axi4delay_2_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_aw_bits_echo_tl_state_source = axi4delay_2_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_w_valid = axi4delay_2_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_w_bits_data = axi4delay_2_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_w_bits_strb = axi4delay_2_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_w_bits_last = axi4delay_2_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_b_ready = axi4delay_2_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_ar_valid = axi4delay_2_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_ar_bits_id = axi4delay_2_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_ar_bits_addr = axi4delay_2_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_ar_bits_len = axi4delay_2_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_ar_bits_size = axi4delay_2_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_ar_bits_burst = axi4delay_2_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_ar_bits_echo_tl_state_size = axi4delay_2_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_ar_bits_echo_tl_state_source = axi4delay_2_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_1_r_ready = axi4delay_2_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_aw_valid = axi4delay_1_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_aw_bits_addr = axi4delay_1_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_aw_bits_len = axi4delay_1_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_aw_bits_size = axi4delay_1_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_aw_bits_burst = axi4delay_1_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_aw_bits_echo_tl_state_size = axi4delay_1_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_aw_bits_echo_tl_state_source = axi4delay_1_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_w_valid = axi4delay_1_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_w_bits_data = axi4delay_1_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_w_bits_strb = axi4delay_1_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_w_bits_last = axi4delay_1_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_b_ready = axi4delay_1_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_ar_valid = axi4delay_1_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_ar_bits_addr = axi4delay_1_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_ar_bits_len = axi4delay_1_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_ar_bits_size = axi4delay_1_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_ar_bits_burst = axi4delay_1_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_ar_bits_echo_tl_state_size = axi4delay_1_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_ar_bits_echo_tl_state_source = axi4delay_1_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_in_0_r_ready = axi4delay_1_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4xbar_auto_out_aw_ready = axi4delay_auto_in_aw_ready; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_w_ready = axi4delay_auto_in_w_ready; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_b_valid = axi4delay_auto_in_b_valid; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_b_bits_id = axi4delay_auto_in_b_bits_id; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_b_bits_resp = axi4delay_auto_in_b_bits_resp; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_b_bits_echo_tl_state_size = axi4delay_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_b_bits_echo_tl_state_source = axi4delay_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_ar_ready = axi4delay_auto_in_ar_ready; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_r_valid = axi4delay_auto_in_r_valid; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_r_bits_id = axi4delay_auto_in_r_bits_id; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_r_bits_data = axi4delay_auto_in_r_bits_data; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_r_bits_resp = axi4delay_auto_in_r_bits_resp; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_r_bits_echo_tl_state_size = axi4delay_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_r_bits_echo_tl_state_source = axi4delay_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 298:16]
  assign axi4xbar_auto_out_r_bits_last = axi4delay_auto_in_r_bits_last; // @[LazyModule.scala 298:16]
  assign slaves_clock = clock;
  assign slaves_reset = reset;
  assign slaves_auto_in_aw_valid = axi4frag_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_aw_bits_id = axi4frag_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_aw_bits_addr = axi4frag_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_aw_bits_echo_tl_state_size = axi4frag_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_aw_bits_echo_tl_state_source = axi4frag_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_aw_bits_echo_real_last = axi4frag_auto_out_aw_bits_echo_real_last; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_w_valid = axi4frag_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_w_bits_data = axi4frag_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_w_bits_strb = axi4frag_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_b_ready = axi4frag_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_ar_valid = axi4frag_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_ar_bits_id = axi4frag_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_ar_bits_addr = axi4frag_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_ar_bits_echo_tl_state_size = axi4frag_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_ar_bits_echo_tl_state_source = axi4frag_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_ar_bits_echo_real_last = axi4frag_auto_out_ar_bits_echo_real_last; // @[LazyModule.scala 296:16]
  assign slaves_auto_in_r_ready = axi4frag_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4frag_clock = clock;
  assign axi4frag_reset = reset;
  assign axi4frag_auto_in_aw_valid = axi4buf_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_aw_bits_id = axi4buf_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_aw_bits_addr = axi4buf_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_aw_bits_len = axi4buf_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_aw_bits_size = axi4buf_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_aw_bits_burst = axi4buf_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_aw_bits_echo_tl_state_size = axi4buf_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_aw_bits_echo_tl_state_source = axi4buf_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_w_valid = axi4buf_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_w_bits_data = axi4buf_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_w_bits_strb = axi4buf_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_w_bits_last = axi4buf_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_b_ready = axi4buf_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_ar_valid = axi4buf_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_ar_bits_id = axi4buf_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_ar_bits_addr = axi4buf_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_ar_bits_len = axi4buf_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_ar_bits_size = axi4buf_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_ar_bits_burst = axi4buf_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_ar_bits_echo_tl_state_size = axi4buf_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_ar_bits_echo_tl_state_source = axi4buf_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_in_r_ready = axi4buf_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_aw_ready = slaves_auto_in_aw_ready; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_w_ready = slaves_auto_in_w_ready; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_b_valid = slaves_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_b_bits_id = slaves_auto_in_b_bits_id; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_b_bits_resp = slaves_auto_in_b_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_b_bits_echo_tl_state_size = slaves_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_b_bits_echo_tl_state_source = slaves_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_b_bits_echo_real_last = slaves_auto_in_b_bits_echo_real_last; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_ar_ready = slaves_auto_in_ar_ready; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_r_valid = slaves_auto_in_r_valid; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_r_bits_id = slaves_auto_in_r_bits_id; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_r_bits_data = slaves_auto_in_r_bits_data; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_r_bits_resp = slaves_auto_in_r_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_r_bits_echo_tl_state_size = slaves_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_r_bits_echo_tl_state_source = slaves_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4frag_auto_out_r_bits_echo_real_last = slaves_auto_in_r_bits_echo_real_last; // @[LazyModule.scala 296:16]
  assign axi4buf_clock = clock;
  assign axi4buf_reset = reset;
  assign axi4buf_auto_in_aw_valid = axi4buf_1_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_aw_bits_id = axi4buf_1_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_aw_bits_addr = axi4buf_1_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_aw_bits_len = axi4buf_1_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_aw_bits_size = axi4buf_1_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_aw_bits_burst = axi4buf_1_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_aw_bits_echo_tl_state_size = axi4buf_1_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_aw_bits_echo_tl_state_source = axi4buf_1_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_w_valid = axi4buf_1_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_w_bits_data = axi4buf_1_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_w_bits_strb = axi4buf_1_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_w_bits_last = axi4buf_1_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_b_ready = axi4buf_1_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_ar_valid = axi4buf_1_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_ar_bits_id = axi4buf_1_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_ar_bits_addr = axi4buf_1_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_ar_bits_len = axi4buf_1_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_ar_bits_size = axi4buf_1_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_ar_bits_burst = axi4buf_1_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_ar_bits_echo_tl_state_size = axi4buf_1_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_ar_bits_echo_tl_state_source = axi4buf_1_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_in_r_ready = axi4buf_1_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_aw_ready = axi4frag_auto_in_aw_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_w_ready = axi4frag_auto_in_w_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_b_valid = axi4frag_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_b_bits_id = axi4frag_auto_in_b_bits_id; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_b_bits_resp = axi4frag_auto_in_b_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_b_bits_echo_tl_state_size = axi4frag_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_b_bits_echo_tl_state_source = axi4frag_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_ar_ready = axi4frag_auto_in_ar_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_r_valid = axi4frag_auto_in_r_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_r_bits_id = axi4frag_auto_in_r_bits_id; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_r_bits_data = axi4frag_auto_in_r_bits_data; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_r_bits_resp = axi4frag_auto_in_r_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_r_bits_echo_tl_state_size = axi4frag_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_r_bits_echo_tl_state_source = axi4frag_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4buf_auto_out_r_bits_last = axi4frag_auto_in_r_bits_last; // @[LazyModule.scala 296:16]
  assign axi4buf_1_clock = clock;
  assign axi4buf_1_reset = reset;
  assign axi4buf_1_auto_in_aw_valid = axi4delay_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_aw_bits_id = axi4delay_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_aw_bits_addr = axi4delay_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_aw_bits_len = axi4delay_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_aw_bits_size = axi4delay_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_aw_bits_burst = axi4delay_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_aw_bits_echo_tl_state_size = axi4delay_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_aw_bits_echo_tl_state_source = axi4delay_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_w_valid = axi4delay_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_w_bits_data = axi4delay_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_w_bits_strb = axi4delay_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_w_bits_last = axi4delay_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_b_ready = axi4delay_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_ar_valid = axi4delay_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_ar_bits_id = axi4delay_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_ar_bits_addr = axi4delay_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_ar_bits_len = axi4delay_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_ar_bits_size = axi4delay_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_ar_bits_burst = axi4delay_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_ar_bits_echo_tl_state_size = axi4delay_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_ar_bits_echo_tl_state_source = axi4delay_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_in_r_ready = axi4delay_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_aw_ready = axi4buf_auto_in_aw_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_w_ready = axi4buf_auto_in_w_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_b_valid = axi4buf_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_b_bits_id = axi4buf_auto_in_b_bits_id; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_b_bits_resp = axi4buf_auto_in_b_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_b_bits_echo_tl_state_size = axi4buf_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_b_bits_echo_tl_state_source = axi4buf_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_ar_ready = axi4buf_auto_in_ar_ready; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_r_valid = axi4buf_auto_in_r_valid; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_r_bits_id = axi4buf_auto_in_r_bits_id; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_r_bits_data = axi4buf_auto_in_r_bits_data; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_r_bits_resp = axi4buf_auto_in_r_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_r_bits_echo_tl_state_size = axi4buf_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_r_bits_echo_tl_state_source = axi4buf_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4buf_1_auto_out_r_bits_last = axi4buf_auto_in_r_bits_last; // @[LazyModule.scala 296:16]
  assign axi4delay_clock = clock;
  assign axi4delay_reset = reset;
  assign axi4delay_auto_in_aw_valid = axi4xbar_auto_out_aw_valid; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_aw_bits_id = axi4xbar_auto_out_aw_bits_id; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_aw_bits_addr = axi4xbar_auto_out_aw_bits_addr; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_aw_bits_len = axi4xbar_auto_out_aw_bits_len; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_aw_bits_size = axi4xbar_auto_out_aw_bits_size; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_aw_bits_burst = axi4xbar_auto_out_aw_bits_burst; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_aw_bits_echo_tl_state_size = axi4xbar_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_aw_bits_echo_tl_state_source = axi4xbar_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_w_valid = axi4xbar_auto_out_w_valid; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_w_bits_data = axi4xbar_auto_out_w_bits_data; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_w_bits_strb = axi4xbar_auto_out_w_bits_strb; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_w_bits_last = axi4xbar_auto_out_w_bits_last; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_b_ready = axi4xbar_auto_out_b_ready; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_ar_valid = axi4xbar_auto_out_ar_valid; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_ar_bits_id = axi4xbar_auto_out_ar_bits_id; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_ar_bits_addr = axi4xbar_auto_out_ar_bits_addr; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_ar_bits_len = axi4xbar_auto_out_ar_bits_len; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_ar_bits_size = axi4xbar_auto_out_ar_bits_size; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_ar_bits_burst = axi4xbar_auto_out_ar_bits_burst; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_ar_bits_echo_tl_state_size = axi4xbar_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_ar_bits_echo_tl_state_source = axi4xbar_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_in_r_ready = axi4xbar_auto_out_r_ready; // @[LazyModule.scala 298:16]
  assign axi4delay_auto_out_aw_ready = axi4buf_1_auto_in_aw_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_w_ready = axi4buf_1_auto_in_w_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_b_valid = axi4buf_1_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_b_bits_id = axi4buf_1_auto_in_b_bits_id; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_b_bits_resp = axi4buf_1_auto_in_b_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_b_bits_echo_tl_state_size = axi4buf_1_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_b_bits_echo_tl_state_source = axi4buf_1_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_ar_ready = axi4buf_1_auto_in_ar_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_r_valid = axi4buf_1_auto_in_r_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_r_bits_id = axi4buf_1_auto_in_r_bits_id; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_r_bits_data = axi4buf_1_auto_in_r_bits_data; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_r_bits_resp = axi4buf_1_auto_in_r_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_r_bits_echo_tl_state_size = axi4buf_1_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_r_bits_echo_tl_state_source = axi4buf_1_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_auto_out_r_bits_last = axi4buf_1_auto_in_r_bits_last; // @[LazyModule.scala 296:16]
  assign masters_clock = clock;
  assign masters_reset = reset;
  assign masters_auto_out_a_ready = model_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign masters_auto_out_d_valid = model_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign masters_auto_out_d_bits_opcode = model_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign masters_auto_out_d_bits_size = model_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign masters_auto_out_d_bits_source = model_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign masters_1_clock = clock;
  assign masters_1_reset = reset;
  assign masters_1_auto_out_a_ready = model_1_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign masters_1_auto_out_d_valid = model_1_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign masters_1_auto_out_d_bits_opcode = model_1_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign masters_1_auto_out_d_bits_size = model_1_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign masters_1_auto_out_d_bits_source = model_1_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign axi4delay_1_clock = clock;
  assign axi4delay_1_reset = reset;
  assign axi4delay_1_auto_in_aw_valid = axi4deint_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_aw_bits_id = axi4deint_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_aw_bits_addr = axi4deint_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_aw_bits_len = axi4deint_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_aw_bits_size = axi4deint_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_aw_bits_burst = axi4deint_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_aw_bits_echo_tl_state_size = axi4deint_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_aw_bits_echo_tl_state_source = axi4deint_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_w_valid = axi4deint_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_w_bits_data = axi4deint_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_w_bits_strb = axi4deint_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_w_bits_last = axi4deint_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_b_ready = axi4deint_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_ar_valid = axi4deint_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_ar_bits_id = axi4deint_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_ar_bits_addr = axi4deint_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_ar_bits_len = axi4deint_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_ar_bits_size = axi4deint_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_ar_bits_burst = axi4deint_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_ar_bits_echo_tl_state_size = axi4deint_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_ar_bits_echo_tl_state_source = axi4deint_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_in_r_ready = axi4deint_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_aw_ready = axi4xbar_auto_in_0_aw_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_w_ready = axi4xbar_auto_in_0_w_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_b_valid = axi4xbar_auto_in_0_b_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_b_bits_id = 1'h0; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_b_bits_resp = axi4xbar_auto_in_0_b_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_b_bits_echo_tl_state_size = axi4xbar_auto_in_0_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_b_bits_echo_tl_state_source = axi4xbar_auto_in_0_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_ar_ready = axi4xbar_auto_in_0_ar_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_r_valid = axi4xbar_auto_in_0_r_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_r_bits_id = 1'h0; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_r_bits_data = axi4xbar_auto_in_0_r_bits_data; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_r_bits_resp = axi4xbar_auto_in_0_r_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_r_bits_echo_tl_state_size = axi4xbar_auto_in_0_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_r_bits_echo_tl_state_source = axi4xbar_auto_in_0_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_1_auto_out_r_bits_last = axi4xbar_auto_in_0_r_bits_last; // @[LazyModule.scala 296:16]
  assign axi4deint_clock = clock;
  assign axi4deint_reset = reset;
  assign axi4deint_auto_in_aw_valid = tl2axi4_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_aw_bits_id = tl2axi4_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_aw_bits_addr = tl2axi4_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_aw_bits_len = tl2axi4_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_aw_bits_size = tl2axi4_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_aw_bits_burst = tl2axi4_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_aw_bits_echo_tl_state_size = tl2axi4_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_aw_bits_echo_tl_state_source = tl2axi4_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_w_valid = tl2axi4_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_w_bits_data = tl2axi4_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_w_bits_strb = tl2axi4_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_w_bits_last = tl2axi4_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_b_ready = tl2axi4_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_ar_valid = tl2axi4_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_ar_bits_id = tl2axi4_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_ar_bits_addr = tl2axi4_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_ar_bits_len = tl2axi4_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_ar_bits_size = tl2axi4_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_ar_bits_burst = tl2axi4_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_ar_bits_echo_tl_state_size = tl2axi4_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_ar_bits_echo_tl_state_source = tl2axi4_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_in_r_ready = tl2axi4_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_aw_ready = axi4delay_1_auto_in_aw_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_w_ready = axi4delay_1_auto_in_w_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_b_valid = axi4delay_1_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_b_bits_resp = axi4delay_1_auto_in_b_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_b_bits_echo_tl_state_size = axi4delay_1_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_b_bits_echo_tl_state_source = axi4delay_1_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_ar_ready = axi4delay_1_auto_in_ar_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_r_valid = axi4delay_1_auto_in_r_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_r_bits_data = axi4delay_1_auto_in_r_bits_data; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_r_bits_resp = axi4delay_1_auto_in_r_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_r_bits_echo_tl_state_size = axi4delay_1_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_r_bits_echo_tl_state_source = axi4delay_1_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4deint_auto_out_r_bits_last = axi4delay_1_auto_in_r_bits_last; // @[LazyModule.scala 296:16]
  assign tl2axi4_clock = clock;
  assign tl2axi4_reset = reset;
  assign tl2axi4_auto_in_a_valid = filter_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_in_a_bits_opcode = filter_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_in_a_bits_size = filter_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_in_a_bits_source = filter_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_in_a_bits_address = filter_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_in_a_bits_mask = filter_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_in_a_bits_data = filter_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_in_d_ready = filter_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_aw_ready = axi4deint_auto_in_aw_ready; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_w_ready = axi4deint_auto_in_w_ready; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_b_valid = axi4deint_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_b_bits_resp = axi4deint_auto_in_b_bits_resp; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_b_bits_echo_tl_state_size = axi4deint_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_b_bits_echo_tl_state_source = axi4deint_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_ar_ready = axi4deint_auto_in_ar_ready; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_r_valid = axi4deint_auto_in_r_valid; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_r_bits_data = axi4deint_auto_in_r_bits_data; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_r_bits_resp = axi4deint_auto_in_r_bits_resp; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_r_bits_echo_tl_state_size = axi4deint_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_r_bits_echo_tl_state_source = axi4deint_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign tl2axi4_auto_out_r_bits_last = axi4deint_auto_in_r_bits_last; // @[LazyModule.scala 296:16]
  assign filter_auto_in_a_valid = model_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign filter_auto_in_a_bits_opcode = model_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign filter_auto_in_a_bits_size = model_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign filter_auto_in_a_bits_source = model_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign filter_auto_in_a_bits_address = model_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign filter_auto_in_a_bits_mask = model_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign filter_auto_in_a_bits_data = model_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign filter_auto_in_d_ready = model_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign filter_auto_out_a_ready = tl2axi4_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign filter_auto_out_d_valid = tl2axi4_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign filter_auto_out_d_bits_opcode = tl2axi4_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign filter_auto_out_d_bits_size = tl2axi4_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign filter_auto_out_d_bits_source = tl2axi4_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign filter_auto_out_d_bits_denied = tl2axi4_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign filter_auto_out_d_bits_data = tl2axi4_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign filter_auto_out_d_bits_corrupt = tl2axi4_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign model_clock = clock;
  assign model_reset = reset;
  assign model_auto_in_a_valid = masters_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign model_auto_in_a_bits_opcode = masters_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign model_auto_in_a_bits_size = masters_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign model_auto_in_a_bits_source = masters_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign model_auto_in_a_bits_address = masters_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign model_auto_in_a_bits_mask = masters_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign model_auto_in_a_bits_data = masters_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign model_auto_out_a_ready = filter_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign model_auto_out_d_valid = filter_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign model_auto_out_d_bits_opcode = filter_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign model_auto_out_d_bits_size = filter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign model_auto_out_d_bits_source = filter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign model_auto_out_d_bits_denied = filter_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign model_auto_out_d_bits_data = filter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign model_auto_out_d_bits_corrupt = filter_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign axi4delay_2_clock = clock;
  assign axi4delay_2_reset = reset;
  assign axi4delay_2_auto_in_aw_valid = axi4deint_1_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_aw_bits_id = axi4deint_1_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_aw_bits_addr = axi4deint_1_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_aw_bits_len = axi4deint_1_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_aw_bits_size = axi4deint_1_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_aw_bits_burst = axi4deint_1_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_aw_bits_echo_tl_state_size = axi4deint_1_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_aw_bits_echo_tl_state_source = axi4deint_1_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_w_valid = axi4deint_1_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_w_bits_data = axi4deint_1_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_w_bits_strb = axi4deint_1_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_w_bits_last = axi4deint_1_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_b_ready = axi4deint_1_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_ar_valid = axi4deint_1_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_ar_bits_id = axi4deint_1_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_ar_bits_addr = axi4deint_1_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_ar_bits_len = axi4deint_1_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_ar_bits_size = axi4deint_1_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_ar_bits_burst = axi4deint_1_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_ar_bits_echo_tl_state_size = axi4deint_1_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_ar_bits_echo_tl_state_source = axi4deint_1_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_in_r_ready = axi4deint_1_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_aw_ready = axi4xbar_auto_in_1_aw_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_w_ready = axi4xbar_auto_in_1_w_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_b_valid = axi4xbar_auto_in_1_b_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_b_bits_id = 1'h0; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_b_bits_resp = axi4xbar_auto_in_1_b_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_b_bits_echo_tl_state_size = axi4xbar_auto_in_1_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_b_bits_echo_tl_state_source = axi4xbar_auto_in_1_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_ar_ready = axi4xbar_auto_in_1_ar_ready; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_r_valid = axi4xbar_auto_in_1_r_valid; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_r_bits_id = 1'h0; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_r_bits_data = axi4xbar_auto_in_1_r_bits_data; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_r_bits_resp = axi4xbar_auto_in_1_r_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_r_bits_echo_tl_state_size = axi4xbar_auto_in_1_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_r_bits_echo_tl_state_source = axi4xbar_auto_in_1_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4delay_2_auto_out_r_bits_last = axi4xbar_auto_in_1_r_bits_last; // @[LazyModule.scala 296:16]
  assign axi4deint_1_clock = clock;
  assign axi4deint_1_reset = reset;
  assign axi4deint_1_auto_in_aw_valid = tl2axi4_1_auto_out_aw_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_aw_bits_id = tl2axi4_1_auto_out_aw_bits_id; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_aw_bits_addr = tl2axi4_1_auto_out_aw_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_aw_bits_len = tl2axi4_1_auto_out_aw_bits_len; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_aw_bits_size = tl2axi4_1_auto_out_aw_bits_size; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_aw_bits_burst = tl2axi4_1_auto_out_aw_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_aw_bits_echo_tl_state_size = tl2axi4_1_auto_out_aw_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_aw_bits_echo_tl_state_source = tl2axi4_1_auto_out_aw_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_w_valid = tl2axi4_1_auto_out_w_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_w_bits_data = tl2axi4_1_auto_out_w_bits_data; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_w_bits_strb = tl2axi4_1_auto_out_w_bits_strb; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_w_bits_last = tl2axi4_1_auto_out_w_bits_last; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_b_ready = tl2axi4_1_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_ar_valid = tl2axi4_1_auto_out_ar_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_ar_bits_id = tl2axi4_1_auto_out_ar_bits_id; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_ar_bits_addr = tl2axi4_1_auto_out_ar_bits_addr; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_ar_bits_len = tl2axi4_1_auto_out_ar_bits_len; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_ar_bits_size = tl2axi4_1_auto_out_ar_bits_size; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_ar_bits_burst = tl2axi4_1_auto_out_ar_bits_burst; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_ar_bits_echo_tl_state_size = tl2axi4_1_auto_out_ar_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_ar_bits_echo_tl_state_source = tl2axi4_1_auto_out_ar_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_in_r_ready = tl2axi4_1_auto_out_r_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_aw_ready = axi4delay_2_auto_in_aw_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_w_ready = axi4delay_2_auto_in_w_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_b_valid = axi4delay_2_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_b_bits_resp = axi4delay_2_auto_in_b_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_b_bits_echo_tl_state_size = axi4delay_2_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_b_bits_echo_tl_state_source = axi4delay_2_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_ar_ready = axi4delay_2_auto_in_ar_ready; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_r_valid = axi4delay_2_auto_in_r_valid; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_r_bits_data = axi4delay_2_auto_in_r_bits_data; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_r_bits_resp = axi4delay_2_auto_in_r_bits_resp; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_r_bits_echo_tl_state_size = axi4delay_2_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_r_bits_echo_tl_state_source = axi4delay_2_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign axi4deint_1_auto_out_r_bits_last = axi4delay_2_auto_in_r_bits_last; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_clock = clock;
  assign tl2axi4_1_reset = reset;
  assign tl2axi4_1_auto_in_a_valid = filter_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_in_a_bits_opcode = filter_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_in_a_bits_size = filter_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_in_a_bits_source = filter_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_in_a_bits_address = filter_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_in_a_bits_mask = filter_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_in_a_bits_data = filter_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_in_d_ready = filter_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_aw_ready = axi4deint_1_auto_in_aw_ready; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_w_ready = axi4deint_1_auto_in_w_ready; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_b_valid = axi4deint_1_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_b_bits_resp = axi4deint_1_auto_in_b_bits_resp; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_b_bits_echo_tl_state_size = axi4deint_1_auto_in_b_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_b_bits_echo_tl_state_source = axi4deint_1_auto_in_b_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_ar_ready = axi4deint_1_auto_in_ar_ready; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_r_valid = axi4deint_1_auto_in_r_valid; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_r_bits_data = axi4deint_1_auto_in_r_bits_data; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_r_bits_resp = axi4deint_1_auto_in_r_bits_resp; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_r_bits_echo_tl_state_size = axi4deint_1_auto_in_r_bits_echo_tl_state_size; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_r_bits_echo_tl_state_source = axi4deint_1_auto_in_r_bits_echo_tl_state_source; // @[LazyModule.scala 296:16]
  assign tl2axi4_1_auto_out_r_bits_last = axi4deint_1_auto_in_r_bits_last; // @[LazyModule.scala 296:16]
  assign filter_1_auto_in_a_valid = model_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign filter_1_auto_in_a_bits_opcode = model_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign filter_1_auto_in_a_bits_size = model_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign filter_1_auto_in_a_bits_source = model_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign filter_1_auto_in_a_bits_address = model_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign filter_1_auto_in_a_bits_mask = model_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign filter_1_auto_in_a_bits_data = model_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign filter_1_auto_in_d_ready = model_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign filter_1_auto_out_a_ready = tl2axi4_1_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign filter_1_auto_out_d_valid = tl2axi4_1_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign filter_1_auto_out_d_bits_opcode = tl2axi4_1_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign filter_1_auto_out_d_bits_size = tl2axi4_1_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign filter_1_auto_out_d_bits_source = tl2axi4_1_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign filter_1_auto_out_d_bits_denied = tl2axi4_1_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign filter_1_auto_out_d_bits_data = tl2axi4_1_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign filter_1_auto_out_d_bits_corrupt = tl2axi4_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign model_1_clock = clock;
  assign model_1_reset = reset;
  assign model_1_auto_in_a_valid = masters_1_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign model_1_auto_in_a_bits_opcode = masters_1_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign model_1_auto_in_a_bits_size = masters_1_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign model_1_auto_in_a_bits_source = masters_1_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign model_1_auto_in_a_bits_address = masters_1_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign model_1_auto_in_a_bits_mask = masters_1_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign model_1_auto_in_a_bits_data = masters_1_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign model_1_auto_out_a_ready = filter_1_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign model_1_auto_out_d_valid = filter_1_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign model_1_auto_out_d_bits_opcode = filter_1_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign model_1_auto_out_d_bits_size = filter_1_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign model_1_auto_out_d_bits_source = filter_1_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign model_1_auto_out_d_bits_denied = filter_1_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign model_1_auto_out_d_bits_data = filter_1_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign model_1_auto_out_d_bits_corrupt = filter_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
endmodule
